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 LINE       35859
 EXPRESSION (addr_hit[334] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T25,T40,T62
1	1	0	Not Covered
1	1	1	Covered	T25,T40,T96

 LINE       35860
 EXPRESSION (addr_hit[334] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T25,T40,T62
1	1	0	Covered	T399,T379,T428
1	1	1	Covered	T25,T40,T463

 LINE       35881
 EXPRESSION (addr_hit[335] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T22,T76
1	1	0	Covered	T379,T519,T520
1	1	1	Covered	T1,T22,T66

 LINE       35946
 EXPRESSION (addr_hit[336] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T75,T172,T416
1	1	0	Covered	T515,T522,T557
1	1	1	Covered	T52,T62,T96

 LINE       35977
 EXPRESSION (addr_hit[337] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T22,T75,T10
1	1	0	Covered	T520,T525,T521
1	1	1	Covered	T52,T62,T96

 LINE       35980
 EXPRESSION (addr_hit[338] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T22,T10,T14
1	1	0	Covered	T379,T525,T521
1	1	1	Covered	T52,T62,T424

 LINE       35983
 EXPRESSION (addr_hit[339] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T22,T10,T14
1	1	0	Covered	T519,T400,T515
1	1	1	Covered	T52,T62,T479

 LINE       35986
 EXPRESSION (addr_hit[340] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T22,T10,T14
1	1	0	Covered	T379,T515,T518
1	1	1	Covered	T52,T62,T424

 LINE       35989
 EXPRESSION (addr_hit[341] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T22,T75,T10
1	1	0	Covered	T379,T518,T438
1	1	1	Covered	T52,T62,T479

 LINE       35992
 EXPRESSION (addr_hit[342] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T22,T75,T10
1	1	0	Covered	T519,T515,T518
1	1	1	Covered	T52,T62,T96

 LINE       35995
 EXPRESSION (addr_hit[343] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T22,T75,T10
1	1	0	Covered	T379,T520,T419
1	1	1	Covered	T52,T62,T96

 LINE       35998
 EXPRESSION (addr_hit[344] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T22,T75
1	1	0	Covered	T515,T517,T438
1	1	1	Covered	T52,T62,T96

 LINE       36001
 EXPRESSION (addr_hit[345] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T75,T10,T172
1	1	0	Covered	T413,T379,T419
1	1	1	Covered	T32,T52,T62

 LINE       36004
 EXPRESSION (addr_hit[346] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T75,T10,T172
1	1	0	Covered	T515,T516,T518
1	1	1	Covered	T32,T250,T399

 LINE       36007
 EXPRESSION (addr_hit[347] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T75,T10,T32
1	1	0	Covered	T520,T538,T558
1	1	1	Covered	T32,T96,T465

 LINE       36010
 EXPRESSION (addr_hit[348] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T379,T519,T520
1	1	1	Covered	T32,T96,T153

 LINE       36013
 EXPRESSION (addr_hit[349] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T75,T10,T32
1	1	0	Covered	T379,T515,T517
1	1	1	Covered	T32,T399,T96

 LINE       36016
 EXPRESSION (addr_hit[350] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T379,T517,T521
1	1	1	Covered	T32,T398,T399

 LINE       36019
 EXPRESSION (addr_hit[351] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T519,T520,T515
1	1	1	Covered	T32,T96,T400

 LINE       36022
 EXPRESSION (addr_hit[352] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T400,T520,T515
1	1	1	Covered	T32,T96,T153

 LINE       36025
 EXPRESSION (addr_hit[353] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T519,T515,T516
1	1	1	Covered	T32,T96,T153

 LINE       36028
 EXPRESSION (addr_hit[354] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T519,T400,T455
1	1	1	Covered	T32,T399,T96

 LINE       36031
 EXPRESSION (addr_hit[355] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T379,T515,T559
1	1	1	Covered	T32,T435,T399

 LINE       36034
 EXPRESSION (addr_hit[356] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T379,T520,T429
1	1	1	Covered	T32,T96,T153

 LINE       36037
 EXPRESSION (addr_hit[357] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T520,T518,T533
1	1	1	Covered	T32,T96,T153

 LINE       36040
 EXPRESSION (addr_hit[358] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T429,T515,T518
1	1	1	Covered	T32,T96,T153

 LINE       36043
 EXPRESSION (addr_hit[359] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T494,T520,T515
1	1	1	Covered	T32,T96,T153

 LINE       36046
 EXPRESSION (addr_hit[360] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T519,T520,T515
1	1	1	Covered	T32,T96,T153

 LINE       36049
 EXPRESSION (addr_hit[361] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T519,T400,T520
1	1	1	Covered	T32,T96,T153

 LINE       36052
 EXPRESSION (addr_hit[362] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T399,T379,T519
1	1	1	Covered	T32,T96,T153

 LINE       36055
 EXPRESSION (addr_hit[363] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T519,T520,T518
1	1	1	Covered	T32,T399,T96

 LINE       36058
 EXPRESSION (addr_hit[364] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T379,T515,T438
1	1	1	Covered	T32,T399,T96

 LINE       36061
 EXPRESSION (addr_hit[365] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T519,T419,T517
1	1	1	Covered	T32,T96,T153

 LINE       36064
 EXPRESSION (addr_hit[366] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T399,T379,T519
1	1	1	Covered	T32,T399,T96

 LINE       36067
 EXPRESSION (addr_hit[367] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T379,T515,T525
1	1	1	Covered	T32,T96,T153

 LINE       36070
 EXPRESSION (addr_hit[368] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T89,T520,T515
1	1	1	Covered	T32,T96,T153

 LINE       36073
 EXPRESSION (addr_hit[369] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T379,T515,T516
1	1	1	Covered	T32,T500,T96

 LINE       36076
 EXPRESSION (addr_hit[370] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T520,T515,T516
1	1	1	Covered	T32,T497,T96

 LINE       36079
 EXPRESSION (addr_hit[371] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T519,T419,T515
1	1	1	Covered	T32,T399,T96

 LINE       36082
 EXPRESSION (addr_hit[372] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T519,T515,T516
1	1	1	Covered	T32,T398,T96

 LINE       36085
 EXPRESSION (addr_hit[373] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T515,T516,T517
1	1	1	Covered	T32,T96,T153

 LINE       36088
 EXPRESSION (addr_hit[374] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T519,T520,T516
1	1	1	Covered	T32,T96,T153

 LINE       36091
 EXPRESSION (addr_hit[375] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T520,T518,T525
1	1	1	Covered	T32,T413,T96

 LINE       36094
 EXPRESSION (addr_hit[376] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T379,T519,T515
1	1	1	Covered	T32,T96,T153

 LINE       36097
 EXPRESSION (addr_hit[377] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T379,T520,T515
1	1	1	Covered	T32,T96,T153

 LINE       36100
 EXPRESSION (addr_hit[378] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T540,T520,T429
1	1	1	Covered	T32,T96,T153

 LINE       36103
 EXPRESSION (addr_hit[379] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T515,T516,T445
1	1	1	Covered	T32,T96,T400

 LINE       36106
 EXPRESSION (addr_hit[380] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T515,T516,T518
1	1	1	Covered	T32,T96,T153

 LINE       36109
 EXPRESSION (addr_hit[381] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T519,T515,T560
1	1	1	Covered	T32,T96,T153

 LINE       36112
 EXPRESSION (addr_hit[382] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T379,T429,T561
1	1	1	Covered	T32,T399,T96

 LINE       36115
 EXPRESSION (addr_hit[383] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T32,T14
1	1	0	Covered	T379,T516,T488
1	1	1	Covered	T32,T96,T153

 LINE       36118
 EXPRESSION (addr_hit[384] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T286,T414
1	1	0	Covered	T428,T515,T516
1	1	1	Covered	T22,T10,T32

 LINE       36121
 EXPRESSION (addr_hit[385] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T286,T87
1	1	0	Covered	T515,T516,T422
1	1	1	Covered	T22,T10,T32

 LINE       36124
 EXPRESSION (addr_hit[386] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T286,T87
1	1	0	Covered	T519,T520,T515
1	1	1	Covered	T22,T10,T32

 LINE       36127
 EXPRESSION (addr_hit[387] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T286,T87
1	1	0	Covered	T399,T400,T515
1	1	1	Covered	T22,T10,T32

 LINE       36130
 EXPRESSION (addr_hit[388] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T286,T414
1	1	0	Covered	T379,T455,T520
1	1	1	Covered	T22,T10,T32

 LINE       36133
 EXPRESSION (addr_hit[389] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T286,T413
1	1	0	Covered	T379,T429,T516
1	1	1	Covered	T22,T10,T32

 LINE       36136
 EXPRESSION (addr_hit[390] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T286,T413
1	1	0	Covered	T379,T515,T477
1	1	1	Covered	T22,T10,T32

 LINE       36139
 EXPRESSION (addr_hit[391] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T286,T413
1	1	0	Covered	T457,T470,T521
1	1	1	Covered	T1,T22,T10

 LINE       36142
 EXPRESSION (addr_hit[392] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T286,T89
1	1	0	Covered	T379,T520,T462
1	1	1	Covered	T10,T32,T14

 LINE       36145
 EXPRESSION (addr_hit[393] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T286,T89
1	1	0	Covered	T519,T520,T515
1	1	1	Covered	T10,T32,T14

 LINE       36148
 EXPRESSION (addr_hit[394] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T286,T414
1	1	0	Covered	T379,T515,T521
1	1	1	Covered	T10,T32,T14

 LINE       36151
 EXPRESSION (addr_hit[395] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T286,T89
1	1	0	Covered	T399,T400,T515
1	1	1	Covered	T10,T32,T14

 LINE       36154
 EXPRESSION (addr_hit[396] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T89,T413
1	1	0	Covered	T515,T438,T562
1	1	1	Covered	T10,T32,T14

 LINE       36157
 EXPRESSION (addr_hit[397] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T412,T504
1	1	0	Covered	T519,T515,T516
1	1	1	Covered	T10,T32,T14

 LINE       36160
 EXPRESSION (addr_hit[398] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T250,T414
1	1	0	Covered	T520,T515,T528
1	1	1	Covered	T10,T32,T14

 LINE       36163
 EXPRESSION (addr_hit[399] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T87,T89
1	1	0	Covered	T400,T429,T542
1	1	1	Covered	T10,T32,T14

 LINE       36166
 EXPRESSION (addr_hit[400] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T86,T89
1	1	0	Covered	T519,T520,T419
1	1	1	Covered	T10,T32,T14

 LINE       36169
 EXPRESSION (addr_hit[401] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T414,T411
1	1	0	Covered	T515,T516,T517
1	1	1	Covered	T10,T32,T14