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71 if (offset < NumSrc) begin : gen_assign
72 185/186 ==> assign vld_tree[Pa] = valid_i[offset];
Tests: T120 T121 T317 | T120 T121 T317 | T120 T121 T317 | T120 T121 T317 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T120 T121 T317 | T24 T122 T123 | T24 T122 T123 | T24 T122 T123 | T24 T122 T123 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T24 T122 T123 | T23 T60 T318 | T23 T60 T318 | T23 T60 T318 | T23 T60 T318 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T23 T60 T318 | T34 T61 T318 | T34 T61 T318 | T34 T61 T318 | T34 T61 T318 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T34 T61 T318 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T3 T205 T168 | T168 T169 | T168 T169 | T168 T169 | T168 T169 | T11 T168 T43 | T168 T169 | T168 T169 | T54 T311 T55 | T54 T311 T55 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T53 T54 T311 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T56 T311 T57 | T56 T311 T57 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T56 T311 T57 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T58 T311 T59 | T58 T311 T59 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T58 T311 T59 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T27 T126 T168 | T168 T169 | T168 T169 | T168 T169 | T168 T169 | T39 T172 T65 | T172 T92 T311 | T76 T311 T320 | T75 T172 T311 | T168 T169 | T168 T169 | T168 T169 | T168 T169 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T1 T22 T19 | T63 T213 T318 | T311 T129 T320 | T311 T338 T320 | T172 T65 T245 | T161 T162 T168 | T168 T169 | T178 T311 T313 | T178 T311 T313 | T311 T323 T320 | T311 T323 T320 | T178 T311 T313 | T311 T320 T321 | T314 T311 T315 | T311 T320 T321 | T311 T320 T321 | T168 T169 | T168 T169 | T168 T169 | T147 T163 T135 | T168 T169 | T311 T320 T321 | T316 T311 T320 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T316 T311 T320 | T311 T320 T321 | T316 T311 T320 | T311 T320 T321
73 assign idx_tree[Pa] = offset;
74 186/186 assign max_tree[Pa] = values_i[offset];
Tests: T251 | T120 T121 T311 | T120 T121 T311 | T120 T121 T311 | T120 T121 T311 | T120 T121 T311 | T120 T121 T311 | T120 T121 T311 | T120 T121 T311 | T120 T121 T311 | T24 T311 T122 | T24 T311 T122 | T24 T311 T122 | T24 T311 T122 | T24 T311 T122 | T24 T311 T122 | T24 T311 T122 | T24 T311 T122 | T24 T311 T122 | T23 T311 T60 | T23 T311 T60 | T23 T311 T60 | T23 T311 T60 | T23 T311 T60 | T23 T311 T60 | T23 T311 T60 | T23 T311 T60 | T23 T311 T60 | T311 T34 T61 | T311 T34 T61 | T311 T34 T61 | T311 T34 T61 | T311 T34 T61 | T311 T34 T61 | T311 T34 T61 | T311 T34 T61 | T311 T34 T61 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T3 T4 T11 | T11 T311 T168 | T11 T311 T168 | T3 T11 T8 | T3 T11 T8 | T11 T311 T168 | T311 T168 T251 | T311 T168 T251 | T54 T311 T55 | T54 T311 T55 | T311 T168 T251 | T54 T311 T55 | T54 T311 T55 | T54 T311 T55 | T54 T311 T55 | T54 T311 T55 | T311 T168 T251 | T53 T54 T311 | T53 T311 T168 | T311 T168 T251 | T53 T311 T168 | T53 T311 T168 | T53 T311 T168 | T56 T311 T57 | T56 T311 T57 | T311 T168 T251 | T56 T311 T57 | T56 T311 T57 | T56 T311 T57 | T56 T311 T57 | T56 T311 T57 | T311 T168 T251 | T56 T311 T57 | T311 T312 T168 | T311 T168 T251 | T311 T312 T168 | T311 T312 T168 | T311 T312 T168 | T58 T311 T59 | T58 T311 T59 | T311 T168 T251 | T58 T311 T59 | T58 T311 T59 | T58 T311 T59 | T58 T311 T59 | T58 T311 T59 | T311 T168 T251 | T58 T311 T59 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T27 T311 T126 | T27 T311 T126 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T39 T75 T76 | T39 T75 T76 | T39 T75 T76 | T39 T75 T76 | T3 T8 T311 | T3 T8 T311 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T1 T22 T19 | T63 T311 T213 | T311 T129 T168 | T39 T75 T76 | T39 T75 T76 | T161 T311 T162 | T311 T168 T251 | T178 T311 T313 | T178 T311 T313 | T178 T311 T313 | T178 T311 T313 | T178 T311 T313 | T311 T168 T251 | T314 T311 T315 | T314 T311 T315 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T147 T163 T311 | T311 T168 T251 | T311 T168 T251 | T316 T311 T168 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T9 T168 | T311 T168 T251 | T311 T168 T251 | T316 T311 T168 | T311 T168 T251 | T316 T311 T168 | T311 T168 T251
75 end else begin : gen_tie_off
76 assign vld_tree[Pa] = '0;
77 assign idx_tree[Pa] = '0;
78 assign max_tree[Pa] = '0;
79 end
80 // This creates the node assignments.
81 end else begin : gen_nodes
82 logic sel; // Local helper variable
83 // In case only one of the parents is valid, forward that one
84 // In case both parents are valid, forward the one with higher value
85 185/185(70 unreachable) assign sel = (~vld_tree[C0] & vld_tree[C1]) |
Tests: T1 T3 T4 | T3 T4 T39 | T4 T24 T23 | T3 T4 T39 | T1 T39 T22 | T24 T23 T120 | T4 T311 T34 | T3 T4 T11 | T39 T27 T58 | T1 T39 T22 | T178 T147 T316 | T24 T120 T121 | T24 T23 T311 | T4 T311 T34 | T4 T311 T168 | T3 T4 T11 | T53 T54 T56 | T58 T56 T311 | T39 T27 T58 | T39 T75 T76 | T1 T22 T19 | T178 T147 T316 | T316 T311 T168 | T120 T121 T311 | T24 T120 T121 | T24 T23 T311 | T23 T311 T34 | T4 T311 T34 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T3 T4 T311 | T3 T11 T8 | T53 T54 T311 | T56 T311 T57 | T56 T311 T57 | T58 T311 T312 | T58 T311 T59 | T39 T27 T172 | T3 T39 T75 | T311 T168 T251 | T311 T168 T251 | T1 T39 T22 | T178 T314 T311 | T147 T316 T163 | T316 T311 T168 | T120 T121 T311 | T120 T121 T311 | T24 T120 T121 | T24 T311 T122 | T24 T23 T311 | T23 T311 T60 | T23 T311 T60 | T311 T34 T61 | T311 T34 T61 | T4 T311 T34 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T3 T4 T11 | T3 T11 T8 | T54 T311 T55 | T54 T311 T55 | T53 T54 T311 | T53 T311 T168 | T56 T311 T57 | T56 T311 T57 | T56 T311 T57 | T58 T311 T312 | T58 T311 T59 | T58 T311 T59 | T58 T311 T59 | T27 T311 T126 | T39 T172 T65 | T39 T75 T76 | T3 T8 T311 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T1 T22 T19 | T39 T75 T76 | T178 T311 T313 | T178 T314 T311 | T311 T168 T251 | T147 T316 T163 | T311 T168 T251 | T316 T311 T168 | T120 T121 T311 | T120 T121 T311 | T120 T121 T311 | T120 T121 T311 | T120 T121 T311 | T24 T311 T122 | T24 T311 T122 | T24 T311 T122 | T24 T311 T122 | T24 T23 T311 | T23 T311 T60 | T23 T311 T60 | T23 T311 T60 | T23 T311 T60 | T311 T34 T61 | T311 T34 T61 | T311 T34 T61 | T311 T34 T61 | T4 T311 T34 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T3 T4 T11 | T11 T311 T168 | T3 T11 T8 | T11 T311 T168 | T54 T311 T55 | T54 T311 T55 | T54 T311 T55 | T54 T311 T55 | T54 T311 T55 | T53 T54 T311 | T53 T311 T168 | T53 T311 T168 | T56 T311 T57 | T56 T311 T57 | T56 T311 T57 | T56 T311 T57 | T56 T311 T57 | T311 T312 T168 | T311 T312 T168 | T58 T311 T312 | T58 T311 T59 | T58 T311 T59 | T58 T311 T59 | T58 T311 T59 | T58 T311 T59 | T311 T168 T251 | T311 T168 T251 | T27 T311 T126 | T311 T168 T251 | T39 T75 T76 | T39 T75 T76 | T3 T39 T75 | T3 T8 T311 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T1 T22 T19 | T63 T311 T129 | T39 T75 T76 | T161 T311 T162 | T178 T311 T313 | T178 T311 T313 | T178 T311 T313 | T314 T311 T315 | T311 T168 T251 | T311 T168 T251 | T147 T163 T311 | T316 T311 T168 | T311 T168 T251 | T311 T9 T168 | T311 T168 T251 | T316 T311 T168 | T316 T311 T168
86 (vld_tree[C0] & vld_tree[C1] & logic'(max_tree[C1] > max_tree[C0]));
87 // Forwarding muxes
88 // Note: these ternaries have triggered a synthesis bug in Vivado versions older
89 // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
90 188/188(67 unreachable) assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
Tests: T1 T3 T4 | T3 T4 T39 | T1 T22 T178 | T4 T24 T23 | T3 T4 T39 | T1 T22 T178 | T24 T23 T120 | T4 T311 T34 | T3 T4 T11 | T39 T27 T58 | T1 T22 T75 | T178 T147 T316 | T24 T120 T121 | T24 T23 T122 | T4 T311 T34 | T4 T311 T320 | T3 T4 T11 | T53 T54 T56 | T58 T56 T311 | T39 T27 T58 | T75 T76 T172 | T1 T22 T19 | T178 T147 T316 | T316 T311 T320 | T120 T121 T317 | T24 T120 T121 | T24 T23 T122 | T23 T34 T61 | T4 T311 T34 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T3 T4 T311 | T11 T54 T311 | T53 T54 T311 | T56 T311 T57 | T56 T311 T57 | T58 T311 T59 | T58 T311 T59 | T39 T27 T172 | T75 T76 T172 | T318 T319 | T318 T319 | T1 T22 T19 | T178 T314 T311 | T147 T316 T163 | T316 T311 T320 | T316 T311 T320 | T120 T121 T317 | T120 T121 T317 | T24 T120 T121 | T24 T122 T123 | T24 T23 T122 | T23 T60 T318 | T23 T60 T318 | T34 T61 T318 | T318 T319 | T4 T311 T34 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T3 T4 T311 | T11 T168 T43 | T54 T311 T55 | T311 T320 T321 | T53 T54 T311 | T311 T320 T321 | T56 T311 T57 | T311 T320 T321 | T56 T311 T57 | T58 T311 T59 | T58 T311 T59 | T311 T320 T321 | T58 T311 T59 | T27 T311 T126 | T39 T172 T65 | T75 T76 T172 | T168 T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T1 T22 T19 | T172 T65 T245 | T178 T311 T313 | T178 T314 T311 | T311 T168 T320 | T147 T316 T163 | T311 T320 T321 | T316 T311 T320 | T316 T311 T320 | T120 T121 T317 | T120 T121 T317 | T120 T121 T317 | T318 T319 | T120 T121 T317 | T24 T122 T123 | T24 T122 T123 | T318 T319 | T318 T319 | T24 T23 T122 | T23 T60 T318 | T23 T60 T318 | T318 T319 | T23 T60 T318 | T34 T61 T318 | T34 T61 T318 | T318 T319 | T318 T319 | T4 T311 T34 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T3 T4 T311 | T168 T169 | T168 T169 | T11 T168 T43 | T54 T311 T55 | T54 T311 T55 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T53 T54 T311 | T311 T320 T321 | T311 T320 T321 | T56 T311 T57 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T56 T311 T57 | T311 T320 T321 | T311 T320 T321 | T58 T311 T59 | T58 T311 T59 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T58 T311 T59 | T311 T320 T321 | T311 T320 T321 | T27 T126 T168 | T168 T169 | T39 T172 T65 | T76 T172 T92 | T75 T172 T311 | T168 T169 | T168 T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T1 T22 T19 | T63 T311 T129 | T172 T65 T245 | T161 T162 T168 | T178 T311 T313 | T311 T323 T320 | T178 T311 T313 | T314 T311 T315 | T311 T168 T320 | T168 T169 | T147 T163 T135 | T316 T311 T320 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T316 T311 T320 | T316 T311 T320
91 188/255 ==> assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
Tests: T1 T3 T4 | T3 T4 T39 | T1 T22 T178 | T4 T24 T23 | T3 T4 T39 | T1 T22 T178 | T24 T23 T120 | T4 T311 T34 | T3 T4 T11 | T39 T27 T58 | T1 T22 T75 | T178 T147 T316 | T24 T120 T121 | T24 T23 T122 | T4 T311 T34 | T4 T311 T320 | T3 T4 T11 | T53 T54 T56 | T58 T56 T311 | T39 T27 T58 | T75 T76 T172 | T1 T22 T19 | T178 T147 T316 | T316 T311 T320 | T120 T121 T317 | T24 T120 T121 | T24 T23 T122 | T23 T34 T61 | T4 T311 T34 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T3 T4 T311 | T11 T54 T311 | T53 T54 T311 | T56 T311 T57 | T56 T311 T57 | T58 T311 T59 | T58 T311 T59 | T39 T27 T172 | T75 T76 T172 | T318 T319 | T318 T319 | T1 T22 T19 | T178 T314 T311 | T147 T316 T163 | T316 T311 T320 | T311 T320 T321 | T120 T121 T317 | T318 T319 | T24 T120 T121 | T24 T122 T123 | T24 T23 T122 | T23 T60 T318 | T23 T60 T318 | T34 T61 T318 | T318 T319 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T3 T205 T168 | T11 T168 T43 | T54 T311 T55 | T311 T320 T321 | T53 T54 T311 | T311 T320 T321 | T56 T311 T57 | T311 T320 T321 | T56 T311 T57 | T58 T311 T59 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T27 T311 T126 | T39 T172 T65 | T75 T76 T172 | T168 T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T1 T22 T19 | T172 T65 T245 | T178 T311 T313 | T314 T311 T315 | T168 T169 | T316 T311 T168 | T311 T320 T321 | T316 T311 T320 | T311 T320 T321 | T120 T121 T317 | T120 T121 T317 | T318 T319 | T318 T319 | T120 T121 T317 | T24 T122 T123 | T24 T122 T123 | T318 T319 | T318 T319 | T23 T60 T318 | T23 T60 T318 | T318 T319 | T318 T319 | T23 T60 T318 | T34 T61 T318 | T34 T61 T318 | T318 T319 | T318 T319 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T4 T311 T320 | T3 T205 T168 | T168 T169 | T168 T169 | T168 T169 | T54 T311 T55 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T56 T311 T57 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T56 T311 T57 | T311 T320 T321 | T311 T320 T321 | T58 T311 T59 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T168 T169 | T168 T169 | T39 T172 T65 | T76 T311 T320 | T168 T169 | T168 T169 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T318 T319 | T1 T22 T19 | T311 T129 T320 | T172 T65 T245 | T168 T169 | T178 T311 T313 | T311 T323 T320 | T311 T320 T321 | T311 T320 T321 | T168 T169 | T168 T169 | T168 T169 | T316 T311 T320 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321 | T311 T320 T321
92 188/255 ==> assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
Tests: T1 T3 T4 | T3 T4 T39 | T1 T39 T22 | T4 T24 T23 | T3 T4 T39 | T1 T39 T22 | T24 T23 T120 | T4 T311 T34 | T3 T4 T11 | T39 T27 T58 | T1 T39 T22 | T178 T147 T316 | T24 T120 T121 | T24 T23 T311 | T4 T311 T34 | T4 T311 T168 | T3 T4 T11 | T53 T54 T56 | T58 T56 T311 | T39 T27 T58 | T39 T75 T76 | T1 T22 T19 | T178 T147 T316 | T316 T311 T168 | T120 T121 T311 | T24 T120 T121 | T24 T23 T311 | T23 T311 T34 | T4 T311 T34 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T3 T4 T311 | T3 T11 T8 | T53 T54 T311 | T56 T311 T57 | T56 T311 T57 | T58 T311 T312 | T58 T311 T59 | T39 T27 T172 | T3 T39 T75 | T311 T168 T251 | T311 T168 T251 | T1 T39 T22 | T178 T314 T311 | T147 T316 T163 | T316 T311 T168 | T316 T311 T168 | T120 T121 T311 | T120 T121 T311 | T24 T120 T121 | T24 T311 T122 | T24 T23 T311 | T23 T311 T60 | T23 T311 T60 | T311 T34 T61 | T311 T34 T61 | T4 T311 T34 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T3 T4 T11 | T3 T11 T8 | T54 T311 T55 | T54 T311 T55 | T53 T54 T311 | T53 T311 T168 | T56 T311 T57 | T56 T311 T57 | T56 T311 T57 | T58 T311 T312 | T58 T311 T59 | T58 T311 T59 | T58 T311 T59 | T27 T311 T126 | T39 T172 T65 | T39 T75 T76 | T3 T8 T311 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T1 T22 T19 | T39 T75 T76 | T178 T311 T313 | T178 T314 T311 | T311 T168 T251 | T147 T316 T163 | T311 T168 T251 | T316 T311 T168 | T316 T311 T168 | T120 T121 T311 | T120 T121 T311 | T120 T121 T311 | T120 T121 T311 | T120 T121 T311 | T24 T311 T122 | T24 T311 T122 | T24 T311 T122 | T24 T311 T122 | T24 T23 T311 | T23 T311 T60 | T23 T311 T60 | T23 T311 T60 | T23 T311 T60 | T311 T34 T61 | T311 T34 T61 | T311 T34 T61 | T311 T34 T61 | T4 T311 T34 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T4 T311 T168 | T3 T4 T11 | T11 T311 T168 | T3 T11 T8 | T11 T311 T168 | T54 T311 T55 | T54 T311 T55 | T54 T311 T55 | T54 T311 T55 | T54 T311 T55 | T53 T54 T311 | T53 T311 T168 | T53 T311 T168 | T56 T311 T57 | T56 T311 T57 | T56 T311 T57 | T56 T311 T57 | T56 T311 T57 | T311 T312 T168 | T311 T312 T168 | T58 T311 T312 | T58 T311 T59 | T58 T311 T59 | T58 T311 T59 | T58 T311 T59 | T58 T311 T59 | T311 T168 T251 | T311 T168 T251 | T27 T311 T126 | T311 T168 T251 | T39 T75 T76 | T39 T75 T76 | T3 T39 T75 | T3 T8 T311 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T311 T168 T251 | T1 T22 T19 | T63 T311 T129 | T39 T75 T76 | T161 T311 T162 | T178 T311 T313 | T178 T311 T313 | T178 T311 T313 | T314 T311 T315 | T311 T168 T251 | T311 T168 T251 | T147 T163 T311 | T316 T311 T168 | T311 T168 T251 | T311 T9 T168 | T311 T168 T251 | T316 T311 T168 | T316 T311 T168
93 end
94 end : gen_level
95 end : gen_tree
96
97
98 // The results can be found at the tree root
99 1/1 assign max_valid_o = vld_tree[0];
Tests: T1 T3 T4
100 1/1 assign max_idx_o = idx_tree[0];
Tests: T1 T3 T4
101 1/1 assign max_value_o = max_tree[0];
Tests: T1 T3 T4
102
103 ////////////////
104 // Assertions //
105 ////////////////
106
107 `ifdef INC_ASSERT
108 //VCS coverage off
109 // pragma coverage off
110
111 // Helper functions for assertions below.
112 function automatic logic [Width-1:0] max_value (input logic [NumSrc-1:0][Width-1:0] values_i,
113 input logic [NumSrc-1:0] valid_i);
114 unreachable logic [Width-1:0] value = '0;
115 unreachable for (int k = 0; k < NumSrc; k++) begin
116 unreachable if (valid_i[k] && values_i[k] > value) begin
117 unreachable value = values_i[k];
118 end
==> MISSING_ELSE
119 end
120 unreachable return value;
121 endfunction : max_value
122
123 function automatic logic [SrcWidth-1:0] max_idx (input logic [NumSrc-1:0][Width-1:0] values_i,
124 input logic [NumSrc-1:0] valid_i);
125 unreachable logic [Width-1:0] value = '0;
126 unreachable logic [SrcWidth-1:0] idx = '0;
127 unreachable for (int k = NumSrc-1; k >= 0; k--) begin
128 unreachable if (valid_i[k] && values_i[k] >= value) begin
129 unreachable value = values_i[k];
130 unreachable idx = k;
131 end
==> MISSING_ELSE
132 end
133 unreachable return idx;
134 endfunction : max_idx
135
136 logic [Width-1:0] max_value_exp;
137 logic [SrcWidth-1:0] max_idx_exp;
138 unreachable assign max_value_exp = max_value(values_i, valid_i);
139 unreachable assign max_idx_exp = max_idx(values_i, valid_i);