CHIP Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: `34b8fc33e3`

Branch: earlgrey_1_0_0_2024_08_20_RC0

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	3.156m	2.990ms	3	3	100.00
		chip_sw_example_rom	1.683m	2.546ms	3	3	100.00
		chip_sw_example_manufacturer	2.801m	3.443ms	3	3	100.00
		chip_sw_example_concurrency	3.362m	3.567ms	2	3	66.67
V1	csr_hw_reset	chip_csr_hw_reset	5.261m	6.677ms	5	5	100.00
V1	csr_rw	chip_csr_rw	11.335m	6.188ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.213h	45.646ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.656h	62.572ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	16.339m	11.166ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.656h	62.572ms	5	5	100.00
		chip_csr_rw	11.335m	6.188ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	14.790s	240.197us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.726m	3.710ms	2	3	66.67
V1	chip_sw_gpio_in	chip_sw_gpio	4.726m	3.710ms	2	3	66.67
V1	chip_sw_gpio_irq	chip_sw_gpio	4.726m	3.710ms	2	3	66.67
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.551m	4.762ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.551m	4.762ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	6.995m	3.952ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	7.099m	4.419ms	4	5	80.00
		chip_sw_uart_tx_rx_idx3	7.913m	4.578ms	4	5	80.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	31.126m	13.353ms	19	20	95.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	29.780m	14.048ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.718m	3.928ms	1	5	20.00
V1		TOTAL			211	220	95.91
V2	chip_pin_mux	chip_padctrl_attributes	3.723m	5.292ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.723m	5.292ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.724m	3.882ms	2	3	66.67
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.629m	5.482ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	4.273m	4.073ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	17.893m	15.379ms	5	5	100.00
		chip_tap_straps_testunlock0	5.965m	6.390ms	5	5	100.00
		chip_tap_straps_rma	6.311m	6.282ms	5	5	100.00
		chip_tap_straps_prod	9.919m	8.908ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	3.574m	3.436ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	13.492m	8.569ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	9.111m	6.028ms	3	6	50.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	9.111m	6.028ms	3	6	50.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.489m	8.321ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	37.440m	21.716ms	1	3	33.33
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en			0	3	0.00
		chip_sw_flash_ctrl_access_jitter_en	11.062m	6.432ms	1	3	33.33
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.336m	18.268ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	3.419m	3.126ms	2	3	66.67
		chip_sw_edn_entropy_reqs_jitter	13.106m	7.394ms	2	3	66.67
		chip_sw_hmac_enc_jitter_en	3.958m	3.097ms	2	3	66.67
		chip_sw_keymgr_key_derivation_jitter_en	29.549m	13.875ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.950m	2.619ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	7.991m	5.025ms	3	3	100.00
		chip_sw_clkmgr_jitter	3.013m	2.491ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.786m	2.865ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	12.030m	6.217ms	3	5	60.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	5.302m	4.875ms	2	3	66.67
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	3.645m	3.630ms	2	3	66.67
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	5.302m	4.875ms	2	3	66.67
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	3.494m	3.072ms	2	3	66.67
		chip_sw_aes_smoketest	3.643m	3.282ms	2	3	66.67
		chip_sw_aon_timer_smoketest	3.813m	3.271ms	2	3	66.67
		chip_sw_clkmgr_smoketest	3.056m	3.599ms	2	3	66.67
		chip_sw_csrng_smoketest	3.191m	2.913ms	3	3	100.00
		chip_sw_entropy_src_smoketest	4.601m	2.946ms	1	3	33.33
		chip_sw_gpio_smoketest	3.795m	2.994ms	3	3	100.00
		chip_sw_hmac_smoketest	3.634m	2.816ms	2	3	66.67
		chip_sw_kmac_smoketest	3.435m	2.485ms	3	3	100.00
		chip_sw_otbn_smoketest			0	3	0.00
		chip_sw_pwrmgr_smoketest	6.365m	7.001ms	2	3	66.67
		chip_sw_pwrmgr_usbdev_smoketest	4.325m	4.831ms	1	3	33.33
		chip_sw_rv_plic_smoketest	2.904m	2.115ms	1	3	33.33
		chip_sw_rv_timer_smoketest	2.849m	2.867ms	3	3	100.00
		chip_sw_rstmgr_smoketest	2.924m	3.072ms	2	3	66.67
		chip_sw_sram_ctrl_smoketest	3.160m	3.514ms	2	3	66.67
		chip_sw_uart_smoketest	3.336m	3.133ms	2	3	66.67
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	3.611m	3.897ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	6.097m	4.723ms	2	3	66.67
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.381h	78.460ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	47.299m	14.988ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	34.068m		0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	7.593m	4.608ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	8.017m	10.207ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.605h	60.429ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.931h	64.720ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	8.759m	5.313ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	8.759m	5.313ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.656h	62.572ms	5	5	100.00
		chip_same_csr_outstanding	58.363m	28.714ms	20	20	100.00
		chip_csr_hw_reset	5.261m	6.677ms	5	5	100.00
		chip_csr_rw	11.335m	6.188ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.656h	62.572ms	5	5	100.00
		chip_same_csr_outstanding	58.363m	28.714ms	20	20	100.00
		chip_csr_hw_reset	5.261m	6.677ms	5	5	100.00
		chip_csr_rw	11.335m	6.188ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.926m	2.438ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	10.780s	58.820us	100	100	100.00
		xbar_smoke_large_delays	2.974m	9.808ms	100	100	100.00
		xbar_smoke_slow_rsp	2.264m	5.776ms	100	100	100.00
		xbar_random_zero_delays	1.210m	608.261us	100	100	100.00
		xbar_random_large_delays	20.148m	105.352ms	100	100	100.00
		xbar_random_slow_rsp	17.867m	67.768ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.146m	1.252ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.099m	1.259ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.854m	2.389ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.099m	1.259ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.761m	3.430ms	100	100	100.00
		xbar_access_same_device_slow_rsp	40.225m	163.061ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.623m	2.499ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	9.976m	15.515ms	100	100	100.00
		xbar_stress_all_with_error	11.421m	19.867ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	14.520m	22.504ms	100	100	100.00
		xbar_stress_all_with_reset_error	15.656m	24.305ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	47.299m	14.988ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	44.398m	30.988ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	45.531m	15.156ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	43.156s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	14.949m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	5.875m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	38.085m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	25.064s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	35.140s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	3.691m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	24.213s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	6.327m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	29.067s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	21.058s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	21.203s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	31.282s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	23.143s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	55.288s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	17.040m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	22.060s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	4.582m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	22.060s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	22.236s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	5.941m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	25.195s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	40.259s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	26.120s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	7.326m		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	8.478m		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	21.184s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	26.376s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	57.718s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	7.338m		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	10.805m		0	3	0.00
		rom_e2e_asm_init_dev	28.261s		0	3	0.00
		rom_e2e_asm_init_prod	20.728m		0	3	0.00
		rom_e2e_asm_init_prod_end	26.302s		0	3	0.00
		rom_e2e_asm_init_rma	28.581m		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	48.831m	15.208ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	49.285m	15.439ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	48.583m	15.749ms	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	56.328m	17.940ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.950m	3.290ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	3.419m	3.126ms	2	3	66.67
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.329m	2.355ms	2	3	66.67
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.148m	3.002ms	2	3	66.67
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	32.874m	13.643ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.575m	18.308ms	1	3	33.33
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.575m	18.308ms	1	3	33.33
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	5.526m	3.799ms	2	3	66.67
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	6.365m	7.001ms	2	3	66.67
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	5.526m	3.799ms	2	3	66.67
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.205m	9.696ms	2	3	66.67
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.205m	9.696ms	2	3	66.67
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	6.233m	6.984ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.020m	5.176ms	2	3	66.67
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	11.029m	5.845ms	2	3	66.67
		chip_sw_aes_idle	3.148m	3.002ms	2	3	66.67
		chip_sw_hmac_enc_idle	4.245m	3.007ms	2	3	66.67
		chip_sw_kmac_idle	3.479m	2.860ms	2	3	66.67
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	6.254m	5.366ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	6.052m	5.706ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	6.193m	5.856ms	2	3	66.67
		chip_sw_clkmgr_off_otbn_trans	5.890m	4.613ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	17.451m	10.585ms	2	3	66.67
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	8.041m	3.977ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.825m	4.259ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	7.420m	3.678ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	7.388m	5.238ms	2	3	66.67
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	7.127m	4.477ms	2	3	66.67
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.868m	5.016ms	1	3	33.33
		chip_sw_ast_clk_outputs	11.489m	8.321ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	12.326m	11.882ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	7.420m	3.678ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	7.388m	5.238ms	2	3	66.67
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en			0	3	0.00
		chip_sw_flash_ctrl_access_jitter_en	11.062m	6.432ms	1	3	33.33
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.336m	18.268ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	3.419m	3.126ms	2	3	66.67
		chip_sw_edn_entropy_reqs_jitter	13.106m	7.394ms	2	3	66.67
		chip_sw_hmac_enc_jitter_en	3.958m	3.097ms	2	3	66.67
		chip_sw_keymgr_key_derivation_jitter_en	29.549m	13.875ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.950m	2.619ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	7.991m	5.025ms	3	3	100.00
		chip_sw_clkmgr_jitter	3.013m	2.491ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.005m	3.104ms	1	3	33.33
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	7.218m	4.869ms	2	3	66.67
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.415m	7.246ms	1	3	33.33
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	49.524m	24.976ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	3.228m	3.580ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.464m	2.623ms	1	3	33.33
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	18.687m	11.881ms	2	3	66.67
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	3.915m	3.253ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.935m	5.400ms	1	3	33.33
		chip_sw_flash_init_reduced_freq	23.353m	26.535ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	5.236h	148.524ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.489m	8.321ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	7.150m	5.095ms	2	3	66.67
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.934m	3.036ms	2	3	66.67
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	8.515m	6.379ms	72	100	72.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	21.609m	8.143ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	15.178m	6.895ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	6.430m	4.880ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	7.730m	6.863ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.579m	3.225ms	2	3	66.67
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.875m	6.506ms	1	3	33.33
		chip_sw_sysrst_ctrl_reset	19.654m	24.651ms	1	3	33.33
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	3.553m	2.998ms	2	3	66.67
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	4.446m	4.377ms	2	3	66.67
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	7.048m	4.658ms	2	3	66.67
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	19.654m	24.651ms	1	3	33.33
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	19.654m	24.651ms	1	3	33.33
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	43.655m	20.820ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	43.655m	20.820ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	6.556m	5.146ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.575m	18.308ms	1	3	33.33
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	2.054h	37.906ms	10	10	100.00
		chip_sw_entropy_src_ast_rng_req	2.663m	2.674ms	2	3	66.67
		chip_sw_edn_entropy_reqs			0	3	0.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.663m	2.674ms	2	3	66.67
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	15.178m	6.895ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test			0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	3.487m	2.909ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	22.213m	23.040ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	11.035m	5.069ms	2	3	66.67
		chip_sw_flash_ctrl_access_jitter_en	11.062m	6.432ms	1	3	33.33
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	7.149m	4.182ms	2	3	66.67
		chip_sw_flash_ctrl_ops_jitter_en			0	3	0.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.070h	43.531ms	2	3	66.67
V2	chip_sw_flash_scramble	chip_sw_flash_init	22.213m	23.040ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	4.433m	3.239ms	2	3	66.67
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	14.859m	7.848ms	2	3	66.67
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.920m	4.687ms	2	3	66.67
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.070h	43.531ms	2	3	66.67
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.920m	4.687ms	2	3	66.67
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.920m	4.687ms	2	3	66.67
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.920m	4.687ms	2	3	66.67
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.920m	4.687ms	2	3	66.67
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	8.515m	6.379ms	72	100	72.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	6.181m	9.433ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	12.133m	5.683ms	2	3	66.67
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	7.926m	5.708ms	2	3	66.67
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	7.926m	5.708ms	2	3	66.67
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.190m	3.346ms	1	3	33.33
		chip_sw_hmac_enc_jitter_en	3.958m	3.097ms	2	3	66.67
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.245m	3.007ms	2	3	66.67
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.979m	3.182ms	3	3	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	20.384m	7.427ms	2	3	66.67
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	10.716m	5.515ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	9.780m	6.047ms	2	3	66.67
		chip_sw_i2c_host_tx_rx_idx2	9.577m	5.892ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.964m	4.170ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	14.859m	7.848ms	2	3	66.67
		chip_sw_keymgr_key_derivation_jitter_en	29.549m	13.875ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	27.758m	11.963ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	32.874m	13.643ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	48.520m	14.920ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.195m	2.588ms	3	3	100.00
		chip_sw_kmac_mode_kmac	3.316m	3.322ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.950m	2.619ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	14.859m	7.848ms	2	3	66.67
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	13.206m	10.435ms	9	15	60.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	3.042m	2.625ms	2	3	66.67
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	2.873m	2.493ms	2	3	66.67
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.479m	2.860ms	2	3	66.67
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	7.455m	6.531ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	17.893m	15.379ms	5	5	100.00
		chip_tap_straps_rma	6.311m	6.282ms	5	5	100.00
		chip_tap_straps_prod	9.919m	8.908ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.340m	3.134ms	1	3	33.33
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	13.206m	10.435ms	9	15	60.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	13.206m	10.435ms	9	15	60.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	13.206m	10.435ms	9	15	60.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod			0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.920m	4.687ms	2	3	66.67
		chip_sw_flash_rma_unlocked	1.070h	43.531ms	2	3	66.67
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	7.089m	4.453ms	2	3	66.67
		chip_sw_otp_ctrl_lc_signals_dev			0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	12.551m	6.672ms	2	3	66.67
		chip_sw_otp_ctrl_lc_signals_rma	12.254m	8.414ms	2	3	66.67
		chip_sw_lc_ctrl_transition	13.206m	10.435ms	9	15	60.00
		chip_sw_keymgr_key_derivation	14.859m	7.848ms	2	3	66.67
		chip_sw_rom_ctrl_integrity_check	5.607m	9.638ms	2	3	66.67
		chip_sw_sram_ctrl_execution_main	10.304m	9.192ms	3	3	100.00
		chip_prim_tl_access	6.181m	9.433ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	12.326m	11.882ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	8.041m	3.977ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.825m	4.259ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	7.420m	3.678ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	7.388m	5.238ms	2	3	66.67
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	7.127m	4.477ms	2	3	66.67
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.868m	5.016ms	1	3	33.33
		chip_tap_straps_dev	17.893m	15.379ms	5	5	100.00
		chip_tap_straps_rma	6.311m	6.282ms	5	5	100.00
		chip_tap_straps_prod	9.919m	8.908ms	5	5	100.00
		chip_rv_dm_lc_disabled	13.060m	16.732ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.801m	4.307ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap			0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap			0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	1.776m	3.739ms	1	3	33.33
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks			0	3	0.00
		chip_rv_dm_lc_disabled	13.060m	16.732ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.285h	47.635ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.254h	51.547ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	11.095m	9.525ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.205h	45.546ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks			0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.717m	2.501ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.528m	2.743ms	3	3	100.00
		rom_volatile_raw_unlock	10.235m		0	3	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	13.206m	10.435ms	9	15	60.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	22.213m	23.040ms	3	3	100.00
		chip_sw_otbn_mem_scramble	5.729m	3.692ms	3	3	100.00
		chip_sw_keymgr_key_derivation	14.859m	7.848ms	2	3	66.67
		chip_sw_sram_ctrl_scrambled_access	7.974m	4.040ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.717m	2.736ms	2	3	66.67
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	22.213m	23.040ms	3	3	100.00
		chip_sw_otbn_mem_scramble	5.729m	3.692ms	3	3	100.00
		chip_sw_keymgr_key_derivation	14.859m	7.848ms	2	3	66.67
		chip_sw_sram_ctrl_scrambled_access	7.974m	4.040ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.717m	2.736ms	2	3	66.67
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	13.206m	10.435ms	9	15	60.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	6.709m	4.141ms	2	3	66.67
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.340m	3.134ms	1	3	33.33
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	7.089m	4.453ms	2	3	66.67
		chip_sw_otp_ctrl_lc_signals_dev			0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	12.551m	6.672ms	2	3	66.67
		chip_sw_otp_ctrl_lc_signals_rma	12.254m	8.414ms	2	3	66.67
		chip_sw_lc_ctrl_transition	13.206m	10.435ms	9	15	60.00
		chip_prim_tl_access	6.181m	9.433ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	6.181m	9.433ms	3	3	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	1.130h	27.652ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	7.523m	8.049ms	2	3	66.67
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	15.621m	21.568ms	1	3	33.33
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.077m	7.620ms	1	3	33.33
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	8.554m	8.870ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	8.687m	8.339ms	2	3	66.67
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	13.622m	25.266ms	1	3	33.33
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	20.268m	18.957ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	10.205m	9.696ms	2	3	66.67
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	16.125m	12.158ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	6.977m	4.312ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	7.523m	8.049ms	2	3	66.67
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.995m	5.289ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	41.648m	33.228ms	1	3	33.33
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	5.027m	7.489ms	2	3	66.67
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.766m	2.995ms	0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	29.723m	20.136ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.875m	6.506ms	1	3	33.33
		chip_sw_pwrmgr_all_reset_reqs	20.835m	13.006ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	34.947m	26.408ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	3.251m	3.191ms	1	3	33.33
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	8.515m	6.379ms	72	100	72.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.607m	9.638ms	2	3	66.67
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.607m	9.638ms	2	3	66.67
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	20.835m	13.006ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	29.723m	20.136ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	6.977m	4.312ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	6.365m	7.001ms	2	3	66.67
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.898m	5.111ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	8.220m	7.257ms	2	3	66.67
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	5.641m	4.694ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	23.039m	13.283ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.124m	3.151ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	8.515m	6.379ms	72	100	72.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	23.367m	9.285ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	12.888m	6.720ms	3	3	100.00
		chip_plic_all_irqs_10	6.512m	3.640ms	2	3	66.67
		chip_plic_all_irqs_20	8.609m	4.363ms	2	3	66.67
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.575m	2.503ms	1	3	33.33
V2	chip_sw_timer	chip_sw_rv_timer_irq	3.669m	3.774ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	47.299m	14.988ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.912m	6.513ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	6.269m	5.083ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	4.278m	3.994ms	2	3	66.67
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.691m	3.409ms	2	3	66.67
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	7.974m	4.040ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	7.991m	5.025ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.407m	7.571ms	1	3	33.33
		chip_sw_sleep_sram_ret_contents_scramble	10.466m	7.379ms	2	3	66.67
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	10.304m	9.192ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	8.515m	6.379ms	72	100	72.00
		chip_sw_data_integrity_escalation	9.111m	6.028ms	3	6	50.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus			0	1	0.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	3.844m	3.045ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup			0	1	0.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx			0	1	0.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host			0	1	0.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.556h	31.707ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	30.330m	12.615ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	3.795m	3.255ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	7.455m	6.531ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	8.515m	6.379ms	72	100	72.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	4.258m	3.019ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	23.039m	13.283ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	5.115m	4.686ms	2	3	66.67
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	6.231m	4.214ms	87	90	96.67
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	16.836m	12.712ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	21.609m	8.143ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	23.367m	9.285ms	3	3	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	16.485m	7.851ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.258h	255.083ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	19.501m	17.715ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	17.194m	13.625ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.898m	5.111ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	6.194m	5.623ms	2	3	66.67
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.814m	6.060ms	2	3	66.67
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	6.311m	6.282ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	13.060m	16.732ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2411	2644	91.19
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.726m	3.200ms	2	3	66.67
V2S		TOTAL			2	3	66.67
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_sw_coremark	chip_sw_coremark	3.739h	71.622ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	16.619m	6.472ms	3	3	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	20.812m	11.428ms	1	1	100.00
		rom_e2e_jtag_debug_dev	19.461m	10.162ms	1	1	100.00
		rom_e2e_jtag_debug_rma	22.247m	10.442ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	59.482m		0	1	0.00
		rom_e2e_jtag_inject_dev	1.151h		0	1	0.00
		rom_e2e_jtag_inject_rma	39.459m		0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.415h	26.118ms	3	3	100.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	4.589m	2.822ms	2	3	66.67
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	6.097m	3.125ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	15.133m	6.266ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	19.556m	8.389ms	2	3	66.67
V3	chip_sw_edn_kat	chip_sw_edn_kat	7.221m	2.946ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	11.240m	5.197ms	1	3	33.33
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.712m	2.769ms	2	3	66.67
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.009m	4.447ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.787m	6.549ms	2	3	66.67
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	6.382m	5.107ms	2	3	66.67
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	20.835m	13.006ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	8.515m	6.379ms	72	100	72.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.703m	3.335ms	3	3	100.00
V3	chip_sw_spi_host_pass_through	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_host_configuration	//sw/device/tests:spi_host_config_test			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_readback	chip_sw_sram_readback			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.551m	4.762ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	51.098m	19.404ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	20.812m	11.428ms	1	1	100.00
		rom_e2e_jtag_debug_dev	19.461m	10.162ms	1	1	100.00
		rom_e2e_jtag_debug_rma	22.247m	10.442ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	6.004m	5.653ms	3	3	100.00
V3		TOTAL			38	51	74.51
	Unmapped tests	chip_sival_flash_info_access	3.447m	3.465ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.104m	4.636ms	2	3	66.67
		chip_sw_otp_ctrl_ecc_error_vendor_test	3.378m	2.402ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	51.563m	16.894ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	11.402m	5.581ms	2	3	66.67
		chip_sw_rv_core_ibex_nmi_irq	9.367m	4.827ms	3	3	100.00
		chip_sw_pwrmgr_lowpower_cancel	5.142m	3.882ms	1	3	33.33
		chip_sw_pwrmgr_sleep_wake_5_bug	6.610m	6.044ms	2	3	66.67
		chip_sw_rv_core_ibex_address_translation	3.490m	3.118ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	3.267m	3.084ms	1	3	33.33
		chip_sw_flash_ctrl_write_clear	4.204m	3.023ms	3	3	100.00
		TOTAL			2688	2951	91.09

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	11	11	6	54.55
V1	18	18	12	66.67
V2	285	270	125	43.86
V2S	1	1	0	0.00
V3	90	23	13	14.44

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.10	95.49	93.88	95.41	--	94.76	97.53	99.53

Failure Buckets

Job timed out after * minutes has 197 failures:
- Test chip_sw_data_integrity_escalation has 3 failures.
  - 0.chip_sw_data_integrity_escalation.108586725537605423617715620358711371293023067739602208262650147858918943438649
    Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log
```
  Job timed out after 60 minutes
```
  - 3.chip_sw_data_integrity_escalation.86381318783727569532334367079969753266216190504831152730323437030474777527047
    Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/3.chip_sw_data_integrity_escalation/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.
- Test chip_sw_uart_tx_rx_idx3 has 1 failures.
  - 0.chip_sw_uart_tx_rx_idx3.30590125956204299821599734526907432466993801616019082086719954495216857015437
    Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx3/latest/run.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_usbdev_vbus has 1 failures.
  - 0.chip_sw_usbdev_vbus.29898425078632510615623597234976075913448900708559758650813292557644265108073
    Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_vbus/latest/run.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_usbdev_aon_pullup has 1 failures.
  - 0.chip_sw_usbdev_aon_pullup.12430002472393506832203578536750102547384166254755027247244803149181003672754
    Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_aon_pullup/latest/run.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_usbdev_setuprx has 1 failures.
  - 0.chip_sw_usbdev_setuprx.77062330126452168756959590767044108062461951884480805810333454847157649336605
    Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_setuprx/latest/run.log
```
  Job timed out after 60 minutes
```
- ... and 120 more tests.

Job returned non-zero exit code has 54 failures:

Test rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1442578684211723915819460686633016372915569764459574941734386093920067483625
Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log

  ERROR: /workspaces/lowrisc/opentitan/WORKSPACE:137:16: fetching bitstreams_repo rule //external:bitstreams: Traceback (most recent call last):
      File "/workspaces/lowrisc/opentitan/rules/bitstreams.bzl", line 85, column 13, in _bitstreams_repo_impl
          fail("Bitstream cache not initialized properly.")
  Error in fail: Bitstream cache not initialized properly.
  ERROR: /workspaces/lowrisc/opentitan/hw/bitstream/BUILD:60:10: //hw/bitstream:bitstream depends on @bitstreams//:chip_earlgrey_cw310_bitstream in repository @bitstreams which failed to fetch. no such package '@bitstreams//': Bitstream cache not initialized properly.
  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted:
  INFO: Elapsed time: 29.091s
  INFO: 0 processes.
  FAILED: Build did NOT complete successfully (3 packages loaded, 21392 targets configured)
  make: *** [/workspaces/lowrisc/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_dev.34356534569073916752086618971171533736893528881224693397718340771051025055373
Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log

  ERROR: /workspaces/lowrisc/opentitan/WORKSPACE:137:16: fetching bitstreams_repo rule //external:bitstreams: Traceback (most recent call last):
      File "/workspaces/lowrisc/opentitan/rules/bitstreams.bzl", line 85, column 13, in _bitstreams_repo_impl
          fail("Bitstream cache not initialized properly.")
  Error in fail: Bitstream cache not initialized properly.
  ERROR: /workspaces/lowrisc/opentitan/hw/bitstream/BUILD:72:10: //hw/bitstream:rom_mmi depends on @bitstreams//:chip_earlgrey_cw310_rom_mmi in repository @bitstreams which failed to fetch. no such package '@bitstreams//': Bitstream cache not initialized properly.
  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted:
  INFO: Elapsed time: 883.420s
  INFO: 0 processes.
  FAILED: Build did NOT complete successfully (0 packages loaded, 21392 targets configured)
  make: *** [/workspaces/lowrisc/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_prod.26606928179554441837174017715987796104171661554760748907205384859678431591687
Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log

  ERROR: /workspaces/lowrisc/opentitan/WORKSPACE:137:16: fetching bitstreams_repo rule //external:bitstreams: Traceback (most recent call last):
      File "/workspaces/lowrisc/opentitan/rules/bitstreams.bzl", line 85, column 13, in _bitstreams_repo_impl
          fail("Bitstream cache not initialized properly.")
  Error in fail: Bitstream cache not initialized properly.
  ERROR: /workspaces/lowrisc/opentitan/hw/bitstream/BUILD:72:10: //hw/bitstream:rom_mmi depends on @bitstreams//:chip_earlgrey_cw310_rom_mmi in repository @bitstreams which failed to fetch. no such package '@bitstreams//': Bitstream cache not initialized properly.
  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted:
  INFO: Elapsed time: 338.321s
  INFO: 0 processes.
  FAILED: Build did NOT complete successfully (0 packages loaded, 21392 targets configured)
  make: *** [/workspaces/lowrisc/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_prod_end has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.84705787561306807419194243775506163998564507939712048394589527213829210376920
Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log

  ERROR: /workspaces/lowrisc/opentitan/WORKSPACE:137:16: fetching bitstreams_repo rule //external:bitstreams: Traceback (most recent call last):
      File "/workspaces/lowrisc/opentitan/rules/bitstreams.bzl", line 85, column 13, in _bitstreams_repo_impl
          fail("Bitstream cache not initialized properly.")
  Error in fail: Bitstream cache not initialized properly.
  ERROR: /workspaces/lowrisc/opentitan/hw/bitstream/BUILD:84:10: //hw/bitstream:otp_mmi depends on @bitstreams//:chip_earlgrey_cw310_otp_mmi in repository @bitstreams which failed to fetch. no such package '@bitstreams//': Bitstream cache not initialized properly.
  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted:
  INFO: Elapsed time: 2270.792s
  INFO: 0 processes.
  FAILED: Build did NOT complete successfully (0 packages loaded, 21392 targets configured)
  make: *** [/workspaces/lowrisc/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_rma has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_rma.114195329547456386597229939460406892985498987784661028184822378557456505636817
Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest/run.log

  ERROR: /workspaces/lowrisc/opentitan/WORKSPACE:137:16: fetching bitstreams_repo rule //external:bitstreams: Traceback (most recent call last):
      File "/workspaces/lowrisc/opentitan/rules/bitstreams.bzl", line 85, column 13, in _bitstreams_repo_impl
          fail("Bitstream cache not initialized properly.")
  Error in fail: Bitstream cache not initialized properly.
  ERROR: /workspaces/lowrisc/opentitan/hw/bitstream/BUILD:72:10: //hw/bitstream:rom_mmi depends on @bitstreams//:chip_earlgrey_cw310_rom_mmi in repository @bitstreams which failed to fetch. no such package '@bitstreams//': Bitstream cache not initialized properly.
  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted:
  INFO: Elapsed time: 11.313s
  INFO: 0 processes.
  FAILED: Build did NOT complete successfully (0 packages loaded, 21392 targets configured)
  make: *** [/workspaces/lowrisc/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 35 more tests.

UVM_ERROR @ * us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A has 4 failures:
- Test chip_sw_pwrmgr_sleep_power_glitch_reset has 2 failures.
  - 0.chip_sw_pwrmgr_sleep_power_glitch_reset.37316220210860728808213748038962294331412138142322558724564361298378900912766
    Line 677, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log
```
  UVM_ERROR @ 2525.276388 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
  UVM_INFO @ 2525.276388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.chip_sw_pwrmgr_sleep_power_glitch_reset.5272953699917364119660976594290031802549519367681872942391534219411602813192
    Line 702, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log
```
  UVM_ERROR @ 2994.918381 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
  UVM_INFO @ 2994.918381 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_random_sleep_power_glitch_reset has 2 failures.
  - 0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.22822794839165918655037641239274623024318045862195544773933416967947367397774
    Line 780, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
```
  UVM_ERROR @ 29030.922844 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
  UVM_INFO @ 29030.922844 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.7564019985132257550458991619107442546678944172078612899294560915943455196393
    Line 550, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
```
  UVM_ERROR @ 15627.398946 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
  UVM_INFO @ 15627.398946 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 3 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 3 failures.
  - 2.chip_sw_alert_handler_lpg_sleep_mode_alerts.36150455450803579547605245573611143367411632422773142428697145121702499302062
    Line 588, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 4214.083758 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
  UVM_INFO @ 4214.083758 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.chip_sw_alert_handler_lpg_sleep_mode_alerts.112581500226987672788271620671408847308940411955687206066765987261314328631377
    Line 594, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3278.830158 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
  UVM_INFO @ 3278.830158 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
- Test chip_sw_all_escalation_resets has 3 failures.
  - 74.chip_sw_all_escalation_resets.41418851618259140217609139298557400588480305705942733958405433206405162495775
    Line 808, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/74.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3158.846616 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3158.846616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 79.chip_sw_all_escalation_resets.5149756963347986108127616132790366461393645985428909886659590034796960288712
    Line 662, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/79.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3207.657730 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3207.657730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:84)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
- Test chip_sw_pwrmgr_lowpower_cancel has 1 failures.
  - 1.chip_sw_pwrmgr_lowpower_cancel.115191469489332399210514562182230045967052128067845585043274512219982658647052
    Line 698, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 2952.931358 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:84)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 2952.931358 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 2.chip_sw_rv_core_ibex_lockstep_glitch.75750858961935056655615523542754795208479292667919369880234677139638785183848
    Line 801, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 3084.024086 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 3084.024086 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```