Unified Coverage Report :: Group :: cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg

Group : cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_errors_cgs_wrap[chip_reg_block]	86.67	1	100	1	64	64

---

Group Instance : tl_errors_cgs_wrap[chip_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance tl_errors_cgs_wrap[chip_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	2	13	86.67

Variables for Group Instance tl_errors_cgs_wrap[chip_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_csr_size_err	2	0	2	100.00	100	1	1	2
cp_instr_type_err	2	0	2	100.00	100	1	1	2
cp_mem_byte_access_err	2	0	2	100.00	100	1	1	2
cp_mem_ro_err	2	0	2	100.00	100	1	1	2
cp_mem_wo_err	2	0	2	100.00	100	1	1	2
cp_tl_protocol_err	1	1	0	0.00	100	1	1	0
cp_unmapped_err	2	0	2	100.00	100	1	1	2
cp_write_w_instr_type_err	2	1	1	50.00	100	1	1	2

Summary for Variable cp_csr_size_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_csr_size_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

925

1

T253

3

T254

3

T255

3

auto[1]

32439

1

T105

478

T547

954

T554

716

---

Summary for Variable cp_instr_type_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_instr_type_err

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	33363	1			T253	3		T254	3		T255	3
auto[1]	1	1			T559	1		-	-		-	-

---

Summary for Variable cp_mem_byte_access_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_mem_byte_access_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33070

1

T253

3

T254

3

T255

3

auto[1]

294

1

T105

12

T547

19

T554

6

---

Summary for Variable cp_mem_ro_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_mem_ro_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33359

1

T253

3

T254

3

T255

3

auto[1]

5

1

T565

1

T558

2

T648

1

---

Summary for Variable cp_mem_wo_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_mem_wo_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32871

1

T253

3

T254

3

T255

3

auto[1]

493

1

T105

15

T547

12

T554

11

---

Summary for Variable cp_tl_protocol_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for cp_tl_protocol_err

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
covered	0	1	1

---

Summary for Variable cp_unmapped_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_unmapped_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33232

1

T105

505

T547

985

T554

733

auto[1]

132

1

T253

3

T254

3

T255

3

---

Summary for Variable cp_write_w_instr_type_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_write_w_instr_type_err

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33364

1

T253

3

T254

3

T255

3