Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3621909	1			T102	79		T103	143		T104	400
values[2]	753359	1			T102	32		T103	51		T104	107
values[3]	123068	1			T102	1		T104	6		T162	2
values[4]	67740	1			T187	1		T548	48		T551	1
values[5]	44737	1			T548	74		T551	4		T456	25
values[6]	32652	1			T548	42		T551	3		T456	26
values[7]	25896	1			T548	65		T551	2		T456	18
values[8]	21725	1			T548	55		T551	2		T456	24
values[9]	19055	1			T548	58		T551	1		T456	29
values[10]	16977	1			T548	77		T456	37		T440	35
values[11]	15368	1			T548	74		T456	20		T440	30
values[12]	14092	1			T548	61		T456	18		T440	14
values[13]	13028	1			T548	58		T456	39		T440	20
values[14]	12510	1			T548	36		T456	33		T440	22
values[15]	12322	1			T548	57		T456	23		T440	21
values[16]	11318	1			T548	73		T456	13		T440	17
values[17]	10965	1			T548	76		T456	21		T440	10
values[18]	10575	1			T548	61		T456	20		T440	9
values[19]	9947	1			T548	54		T456	23		T440	9
values[20]	9834	1			T548	64		T456	40		T440	9
values[21]	9382	1			T548	46		T456	24		T440	10
values[22]	9254	1			T548	49		T456	20		T440	12
values[23]	8906	1			T548	66		T456	14		T440	9
values[24]	8615	1			T548	60		T456	17		T440	9
values[25]	8115	1			T548	64		T456	22		T440	8
values[26]	7977	1			T548	52		T456	17		T440	6
values[27]	7947	1			T548	55		T456	14		T440	15
values[28]	7358	1			T548	35		T456	12		T440	8
values[29]	6881	1			T548	27		T456	9		T440	19
values[30]	6675	1			T548	32		T456	12		T440	5
values[31]	6384	1			T548	33		T456	24		T440	3
values[32]	5590	1			T548	44		T456	24		T440	3
values[33]	4909	1			T548	18		T456	13		T440	8
values[34]	4714	1			T548	10		T456	6		T440	7
values[35]	4452	1			T548	15		T456	10		T440	5
values[36]	4272	1			T548	12		T456	6		T440	1
values[37]	4149	1			T548	11		T456	11		T440	2
values[38]	3985	1			T548	14		T456	7		T440	1
values[39]	3774	1			T548	11		T456	4		T440	1
values[40]	3705	1			T548	8		T456	1		T440	2
values[41]	3566	1			T548	1		T456	3		T440	1
values[42]	3505	1			T548	3		T456	1		T440	1
values[43]	3447	1			T548	3		T456	1		T440	1
values[44]	3476	1			T548	2		T456	2		T440	3
values[45]	3430	1			T548	2		T456	2		T440	2
values[46]	3285	1			T548	1		T456	1		T440	5
values[47]	3214	1			T548	1		T456	2		T440	1
values[48]	3098	1			T548	6		T456	9		T440	1
values[49]	3110	1			T548	1		T456	1		T440	1
values[50]	3118	1			T548	5		T456	1		T440	1
values[51]	2975	1			T548	1		T456	1		T440	1
values[52]	2951	1			T548	5		T456	2		T440	3
values[53]	2867	1			T548	2		T456	2		T440	2
values[54]	2768	1			T548	5		T456	1		T440	1
values[55]	2734	1			T548	3		T456	1		T440	1
values[56]	2709	1			T548	4		T456	4		T440	1
values[57]	2774	1			T548	1		T456	1		T440	6
values[58]	2734	1			T548	9		T456	3		T440	2
values[59]	2696	1			T548	1		T456	2		T440	2
values[60]	2712	1			T456	1		T440	1		T677	7
values[61]	3017	1			T456	1		T440	1		T677	4
values[62]	4576	1			T456	1		T440	1		T677	3
values[63]	12303	1			T456	1		T440	1		T677	34
values[64]	245302	1			T456	141		T440	162		T677	166

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4734991	1			T102	102		T103	75		T104	507
values[2]	809754	1			T102	29		T103	24		T104	129
values[3]	87497	1			T102	1		T103	1		T104	23
values[4]	15508	1			T104	3		T187	1		T163	1
values[5]	5954	1			T456	6		T440	3		T459	6
values[6]	3999	1			T456	2		T440	3		T459	1
values[7]	2975	1			T456	5		T440	3		T459	1
values[8]	2525	1			T456	4		T440	6		T677	1
values[9]	2217	1			T456	5		T440	3		T677	4
values[10]	1969	1			T456	2		T440	4		T677	1
values[11]	1737	1			T456	6		T440	3		T677	1
values[12]	1647	1			T456	4		T440	3		T677	2
values[13]	1554	1			T456	3		T440	3		T677	4
values[14]	1536	1			T456	4		T440	5		T677	5
values[15]	1353	1			T456	3		T440	6		T677	3
values[16]	1221	1			T456	4		T440	3		T677	1
values[17]	1191	1			T456	6		T440	3		T677	1
values[18]	1036	1			T456	5		T440	3		T677	1
values[19]	943	1			T456	3		T440	4		T677	2
values[20]	920	1			T456	2		T440	3		T677	1
values[21]	910	1			T456	5		T440	3		T677	3
values[22]	844	1			T456	4		T440	6		T677	2
values[23]	803	1			T456	4		T440	3		T677	2
values[24]	749	1			T456	3		T440	5		T677	1
values[25]	754	1			T456	3		T440	6		T677	1
values[26]	726	1			T456	3		T440	4		T677	1
values[27]	684	1			T456	5		T440	2		T677	2
values[28]	609	1			T456	3		T440	4		T677	1
values[29]	641	1			T456	3		T440	4		T677	2
values[30]	685	1			T456	4		T440	3		T677	2
values[31]	663	1			T456	3		T440	3		T677	2
values[32]	629	1			T456	3		T440	6		T677	3
values[33]	597	1			T456	3		T440	3		T677	4
values[34]	596	1			T456	4		T440	4		T677	5
values[35]	562	1			T456	3		T440	6		T677	2
values[36]	552	1			T456	3		T440	5		T677	4
values[37]	531	1			T456	3		T440	4		T677	9
values[38]	480	1			T456	3		T440	3		T677	5
values[39]	478	1			T456	3		T440	5		T677	2
values[40]	470	1			T456	7		T440	6		T677	2
values[41]	467	1			T456	3		T440	7		T677	2
values[42]	481	1			T456	6		T440	3		T677	2
values[43]	490	1			T456	3		T440	4		T677	2
values[44]	511	1			T456	3		T440	4		T677	3
values[45]	461	1			T456	6		T440	3		T677	3
values[46]	447	1			T456	4		T440	4		T677	3
values[47]	416	1			T456	6		T440	3		T677	1
values[48]	411	1			T456	4		T440	9		T677	1
values[49]	368	1			T456	2		T440	3		T677	1
values[50]	421	1			T456	2		T440	4		T677	1
values[51]	411	1			T456	3		T440	7		T677	1
values[52]	404	1			T456	3		T440	3		T677	1
values[53]	414	1			T456	3		T440	3		T677	1
values[54]	408	1			T456	3		T440	3		T677	1
values[55]	390	1			T456	3		T440	3		T677	1
values[56]	390	1			T456	7		T440	3		T677	1
values[57]	361	1			T456	4		T440	3		T677	1
values[58]	379	1			T456	6		T440	9		T677	1
values[59]	356	1			T456	2		T440	5		T677	2
values[60]	364	1			T456	2		T440	4		T677	1
values[61]	431	1			T456	5		T440	3		T677	1
values[62]	707	1			T456	5		T440	4		T677	4
values[63]	2776	1			T456	9		T440	8		T677	33
values[64]	26602	1			T456	297		T440	206		T677	84

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	552012	1			T102	2		T103	1		T104	5
values[2]	2549757	1			T102	25		T103	71		T104	379
values[3]	1213365	1			T102	141		T103	40		T104	126
values[4]	167084	1			T102	2		T162	1		T187	3
values[5]	86313	1			T548	61		T551	2		T456	45
values[6]	56328	1			T548	56		T551	1		T456	29
values[7]	39900	1			T548	50		T551	2		T456	33
values[8]	31706	1			T548	60		T551	2		T456	41
values[9]	26331	1			T548	61		T551	2		T456	32
values[10]	22639	1			T548	47		T551	1		T456	24
values[11]	20517	1			T548	59		T551	4		T456	12
values[12]	18596	1			T548	57		T551	2		T456	14
values[13]	17113	1			T548	66		T456	17		T440	1
values[14]	15917	1			T548	50		T456	18		T440	2
values[15]	14774	1			T548	61		T456	32		T440	7
values[16]	13814	1			T548	62		T456	26		T440	5
values[17]	13406	1			T548	50		T456	23		T440	12
values[18]	12870	1			T548	64		T456	17		T440	9
values[19]	12120	1			T548	72		T456	21		T440	3
values[20]	11468	1			T548	57		T456	28		T440	6
values[21]	11223	1			T548	54		T456	28		T440	8
values[22]	10660	1			T548	74		T456	19		T440	8
values[23]	10299	1			T548	75		T456	32		T440	8
values[24]	9574	1			T548	54		T456	37		T440	5
values[25]	9316	1			T548	38		T456	20		T440	7
values[26]	9109	1			T548	64		T456	18		T440	4
values[27]	8618	1			T548	64		T456	29		T440	12
values[28]	8228	1			T548	64		T456	23		T440	19
values[29]	7598	1			T548	40		T456	16		T440	15
values[30]	7247	1			T548	62		T456	11		T440	13
values[31]	6733	1			T548	51		T456	5		T440	7
values[32]	6292	1			T548	36		T456	16		T440	4
values[33]	5902	1			T548	27		T456	5		T440	3
values[34]	5344	1			T548	22		T456	5		T440	1
values[35]	5243	1			T548	22		T456	6		T440	8
values[36]	4910	1			T548	17		T456	6		T440	11
values[37]	4570	1			T548	16		T456	15		T440	4
values[38]	4227	1			T548	10		T456	17		T440	5
values[39]	4139	1			T548	13		T456	5		T440	1
values[40]	4057	1			T548	13		T456	4		T440	1
values[41]	3997	1			T548	5		T456	3		T440	1
values[42]	3774	1			T548	8		T456	5		T440	4
values[43]	3694	1			T548	7		T456	4		T440	4
values[44]	3760	1			T548	10		T456	2		T440	3
values[45]	3770	1			T548	6		T456	4		T440	1
values[46]	3670	1			T548	12		T456	3		T440	2
values[47]	3617	1			T548	4		T456	10		T440	1
values[48]	3522	1			T548	4		T456	10		T440	3
values[49]	3321	1			T548	4		T456	3		T440	2
values[50]	3518	1			T548	9		T456	6		T440	3
values[51]	3391	1			T548	10		T456	3		T440	1
values[52]	3235	1			T548	1		T456	1		T677	4
values[53]	3231	1			T548	2		T456	2		T677	7
values[54]	3258	1			T456	1		T677	17		T643	2
values[55]	3196	1			T456	3		T677	10		T643	2
values[56]	3134	1			T677	6		T643	2		T542	23
values[57]	3073	1			T677	4		T643	2		T542	22
values[58]	2949	1			T677	10		T643	2		T542	22
values[59]	2997	1			T677	4		T643	2		T542	30
values[60]	2970	1			T677	8		T643	2		T542	21
values[61]	3006	1			T677	7		T643	2		T542	28
values[62]	4052	1			T677	8		T643	2		T542	48
values[63]	10501	1			T677	31		T643	3		T542	141
values[64]	234644	1			T677	174		T643	437		T542	492