Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2355129	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

38835943

1

T1

350

T2

3132

T3

3461

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	29167976	1			T1	175		T2	607		T3	842
values[0x0]	10533899	1			T1	175		T2	2525		T3	2619
values[0x1]	1489197	1			T1	3		T2	71		T3	118

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	914148	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40276924

1

T1

353

T2

3203

T3

3579

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19026451	1			T1	177		T2	1602		T3	1790
valid_sources[0x01]	19024719	1			T1	176		T2	1601		T3	1789
valid_sources[0x02]	50666	1			T41	1		T243	1		T81	1
valid_sources[0x03]	53092	1			T81	1		T105	7		T642	679
valid_sources[0x04]	51428	1			T41	1		T64	3		T105	13
valid_sources[0x05]	49711	1			T64	2		T105	10		T642	512
valid_sources[0x06]	50614	1			T243	1		T81	1		T105	9
valid_sources[0x07]	50991	1			T41	1		T105	12		T642	896
valid_sources[0x08]	50378	1			T41	2		T243	1		T105	7
valid_sources[0x09]	51126	1			T65	1		T105	7		T642	768
valid_sources[0x0a]	50631	1			T64	2		T65	1		T81	1
valid_sources[0x0b]	49637	1			T41	2		T64	2		T65	1
valid_sources[0x0c]	50657	1			T41	1		T65	1		T81	1
valid_sources[0x0d]	52425	1			T41	2		T65	1		T243	1
valid_sources[0x0e]	51329	1			T64	1		T105	16		T642	128
valid_sources[0x0f]	50707	1			T65	2		T81	1		T105	16
valid_sources[0x10]	50966	1			T64	2		T65	1		T81	2
valid_sources[0x11]	51482	1			T65	1		T105	13		T642	512
valid_sources[0x12]	50396	1			T64	1		T243	1		T81	1
valid_sources[0x13]	49855	1			T64	1		T65	2		T105	16
valid_sources[0x14]	50375	1			T41	1		T243	1		T105	11
valid_sources[0x15]	51335	1			T41	1		T64	2		T105	11
valid_sources[0x16]	50231	1			T64	1		T243	2		T105	20
valid_sources[0x17]	50316	1			T41	1		T65	1		T243	1
valid_sources[0x18]	49960	1			T41	1		T81	1		T105	10
valid_sources[0x19]	50873	1			T41	1		T81	1		T105	12
valid_sources[0x1a]	50458	1			T64	1		T65	1		T105	7
valid_sources[0x1b]	50119	1			T64	2		T81	2		T105	11
valid_sources[0x1c]	51287	1			T65	1		T243	1		T81	1
valid_sources[0x1d]	50132	1			T105	17		T642	640		T176	63
valid_sources[0x1e]	50085	1			T64	1		T243	1		T105	11
valid_sources[0x1f]	50668	1			T41	2		T81	1		T105	23
valid_sources[0x20]	50555	1			T41	2		T105	16		T642	256

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28073957

1

T1

175

T2

607

T3

842

values[0x0]

all_enables

biggest_size

10483378

1

T1

175

T2

2525

T3

2619

values[0x1]

all_enables

biggest_size

278608

1

T41

23

T64

20

T65

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2814801	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

444067

1

T102

8

T103

26

T104

64

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1103119	1			T102	42		T103	61		T104	152
values[0x0]	1051015	1			T102	32		T103	64		T104	178
values[0x1]	1104734	1			T102	38		T103	69		T104	183

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2177343	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1081525

1

T102

40

T103

74

T104

159

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51412	1			T104	5		T162	12		T187	6
valid_sources[0x01]	50956	1			T102	2		T104	7		T162	9
valid_sources[0x02]	51232	1			T103	5		T104	5		T162	13
valid_sources[0x03]	50514	1			T102	2		T103	3		T104	3
valid_sources[0x04]	51069	1			T102	5		T103	6		T162	15
valid_sources[0x05]	50212	1			T103	12		T104	2		T162	8
valid_sources[0x06]	52114	1			T102	7		T103	2		T104	29
valid_sources[0x07]	50140	1			T104	10		T162	10		T163	2
valid_sources[0x08]	50787	1			T102	3		T103	9		T104	11
valid_sources[0x09]	50993	1			T102	1		T103	3		T104	4
valid_sources[0x0a]	50470	1			T102	2		T103	3		T104	13
valid_sources[0x0b]	50819	1			T104	2		T162	12		T163	4
valid_sources[0x0c]	51218	1			T103	4		T104	6		T162	11
valid_sources[0x0d]	50619	1			T102	2		T103	2		T104	18
valid_sources[0x0e]	51092	1			T104	5		T162	14		T411	12
valid_sources[0x0f]	49804	1			T103	2		T104	11		T162	15
valid_sources[0x10]	50946	1			T102	5		T103	9		T104	2
valid_sources[0x11]	51273	1			T103	1		T104	11		T162	23
valid_sources[0x12]	51120	1			T104	9		T162	19		T411	14
valid_sources[0x13]	50953	1			T102	2		T103	5		T104	1
valid_sources[0x14]	51382	1			T102	8		T103	2		T104	14
valid_sources[0x15]	51856	1			T103	1		T104	3		T162	21
valid_sources[0x16]	49764	1			T103	1		T104	10		T162	17
valid_sources[0x17]	50812	1			T102	3		T103	5		T104	5
valid_sources[0x18]	50828	1			T102	3		T103	6		T104	11
valid_sources[0x19]	51589	1			T104	9		T162	14		T187	6
valid_sources[0x1a]	51773	1			T102	2		T103	4		T104	8
valid_sources[0x1b]	49683	1			T102	5		T103	1		T104	1
valid_sources[0x1c]	51697	1			T103	6		T162	14		T187	5
valid_sources[0x1d]	50367	1			T103	5		T104	10		T162	12
valid_sources[0x1e]	51099	1			T102	6		T103	1		T104	17
valid_sources[0x1f]	50363	1			T102	2		T103	5		T104	10
valid_sources[0x20]	50803	1			T102	2		T104	6		T162	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46532

1

T102

2

T103

1

T104

4

values[0x0]

all_enables

biggest_size

350711

1

T102

4

T103

25

T104

52

values[0x1]

all_enables

biggest_size

46824

1

T102

2

T104

8

T162

8

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3004629	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

489249

1

T102

19

T103

14

T104

89

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1194626	1			T102	41		T103	38		T104	230
values[0x0]	1101772	1			T102	40		T103	26		T104	216
values[0x1]	1197480	1			T102	51		T103	36		T104	216

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2305720	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1188158

1

T102

53

T103

40

T104

229

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54126	1			T102	8		T103	2		T104	17
valid_sources[0x01]	53815	1			T102	1		T104	8		T162	14
valid_sources[0x02]	54543	1			T102	3		T103	4		T104	10
valid_sources[0x03]	55246	1			T103	5		T104	7		T162	4
valid_sources[0x04]	55889	1			T102	5		T104	10		T162	9
valid_sources[0x05]	54597	1			T102	3		T103	4		T104	12
valid_sources[0x06]	54868	1			T102	1		T103	2		T104	4
valid_sources[0x07]	54960	1			T102	6		T103	3		T104	17
valid_sources[0x08]	53572	1			T102	1		T103	1		T104	5
valid_sources[0x09]	55864	1			T103	1		T104	8		T162	9
valid_sources[0x0a]	55414	1			T102	2		T104	5		T162	14
valid_sources[0x0b]	54811	1			T102	2		T103	1		T104	8
valid_sources[0x0c]	54761	1			T102	2		T104	15		T162	7
valid_sources[0x0d]	54915	1			T102	2		T104	10		T162	12
valid_sources[0x0e]	54966	1			T102	2		T103	1		T104	11
valid_sources[0x0f]	54232	1			T103	1		T104	7		T162	11
valid_sources[0x10]	53713	1			T102	3		T103	1		T104	9
valid_sources[0x11]	54342	1			T102	2		T103	1		T104	14
valid_sources[0x12]	53887	1			T102	1		T103	5		T104	8
valid_sources[0x13]	54487	1			T102	1		T103	1		T104	11
valid_sources[0x14]	54229	1			T102	1		T103	1		T104	13
valid_sources[0x15]	54366	1			T102	3		T104	26		T162	16
valid_sources[0x16]	55250	1			T102	2		T103	2		T104	5
valid_sources[0x17]	53744	1			T103	3		T104	6		T162	20
valid_sources[0x18]	54765	1			T102	1		T104	10		T162	11
valid_sources[0x19]	54275	1			T102	2		T103	1		T104	9
valid_sources[0x1a]	53656	1			T102	1		T104	10		T162	11
valid_sources[0x1b]	54427	1			T102	2		T103	1		T104	8
valid_sources[0x1c]	55194	1			T102	1		T104	11		T162	19
valid_sources[0x1d]	54965	1			T102	4		T103	2		T104	9
valid_sources[0x1e]	53979	1			T103	1		T104	10		T162	6
valid_sources[0x1f]	53252	1			T102	4		T103	1		T104	10
valid_sources[0x20]	54947	1			T103	1		T104	10		T162	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51301

1

T102

3

T104

8

T162

10

values[0x0]

all_enables

biggest_size

386698

1

T102

14

T103

13

T104

72

values[0x1]

all_enables

biggest_size

51250

1

T102

2

T103

1

T104

9

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2842941	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

449025

1

T102

22

T103

19

T104

67

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1114187	1			T102	60		T103	28		T104	172
values[0x0]	1061649	1			T102	64		T103	45		T104	171
values[0x1]	1116130	1			T102	46		T103	39		T104	167

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2200503	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1091463

1

T102

44

T103

37

T104

158

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51198	1			T102	8		T103	4		T104	7
valid_sources[0x01]	50626	1			T104	9		T162	8		T187	4
valid_sources[0x02]	51616	1			T102	10		T103	3		T104	8
valid_sources[0x03]	51336	1			T102	5		T103	1		T104	9
valid_sources[0x04]	51005	1			T104	6		T162	21		T187	2
valid_sources[0x05]	51712	1			T102	2		T103	2		T104	6
valid_sources[0x06]	51882	1			T102	4		T162	20		T163	3
valid_sources[0x07]	52734	1			T104	8		T162	13		T187	3
valid_sources[0x08]	50914	1			T103	6		T104	13		T162	10
valid_sources[0x09]	51602	1			T102	13		T104	4		T162	14
valid_sources[0x0a]	51503	1			T103	3		T104	2		T162	13
valid_sources[0x0b]	50789	1			T103	2		T104	2		T162	17
valid_sources[0x0c]	51988	1			T103	4		T104	2		T162	15
valid_sources[0x0d]	50983	1			T102	4		T104	1		T162	31
valid_sources[0x0e]	50665	1			T103	2		T104	20		T162	8
valid_sources[0x0f]	51883	1			T102	1		T104	6		T162	13
valid_sources[0x10]	51464	1			T103	2		T104	35		T162	8
valid_sources[0x11]	51349	1			T103	4		T104	29		T162	11
valid_sources[0x12]	51065	1			T103	4		T104	3		T162	15
valid_sources[0x13]	51944	1			T104	19		T162	8		T187	2
valid_sources[0x14]	51967	1			T102	1		T104	2		T162	12
valid_sources[0x15]	51461	1			T162	10		T163	1		T550	6
valid_sources[0x16]	51285	1			T102	7		T104	21		T162	16
valid_sources[0x17]	51606	1			T102	1		T103	6		T104	10
valid_sources[0x18]	50798	1			T102	9		T104	6		T162	14
valid_sources[0x19]	51936	1			T104	6		T162	6		T550	26
valid_sources[0x1a]	52413	1			T103	1		T104	3		T162	12
valid_sources[0x1b]	50504	1			T103	6		T104	18		T162	12
valid_sources[0x1c]	51709	1			T102	6		T162	17		T187	1
valid_sources[0x1d]	51861	1			T103	1		T104	3		T162	19
valid_sources[0x1e]	50584	1			T104	12		T162	17		T550	2
valid_sources[0x1f]	50380	1			T103	1		T104	2		T162	12
valid_sources[0x20]	50912	1			T103	3		T162	15		T187	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47224

1

T102

3

T103

3

T104

5

values[0x0]

all_enables

biggest_size

354404

1

T102

19

T103

15

T104

55

values[0x1]

all_enables

biggest_size

47397

1

T103

1

T104

7

T162

10