Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
45.52 52.63 38.46 45.45


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.10 66.67 45.45 68.18


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.20 99.12 87.34 98.84 83.68 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter 76.27 82.35 55.56 90.91



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
45.52 52.63 38.46 45.45


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
56.14 63.89 40.91 63.64


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.20 99.12 87.34 98.84 83.68 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter 67.58 76.47 44.44 81.82



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
45.52 52.63 38.46 45.45


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
56.14 63.89 40.91 63.64


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.20 99.12 87.34 98.84 83.68 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter 67.58 76.47 44.44 81.82



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.28 63.16 69.23 45.45


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.34 80.56 77.27 68.18


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.20 99.12 87.34 98.84 83.68 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter 93.27 100.00 88.89 90.91



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
61.50 68.42 61.54 54.55


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.26 83.33 72.73 72.73


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.20 99.12 87.34 98.84 83.68 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter 93.27 100.00 88.89 90.91



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.07 68.42 69.23 54.55


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.78 83.33 77.27 72.73


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.20 99.12 87.34 98.84 83.68 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter 93.27 100.00 88.89 90.91



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.07 68.42 69.23 54.55


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.81 83.33 81.82 77.27


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.20 99.12 87.34 98.84 83.68 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter 100.00 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.33 78.95 92.31 72.73


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.24 88.89 95.45 86.36


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.20 99.12 87.34 98.84 83.68 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter 100.00 100.00 100.00 100.00

Line Coverage for Module : pinmux_wkup
Line No.TotalCoveredPercent
TOTAL191578.95
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN5011100.00
CONT_ASSIGN5211100.00
ALWAYS5510660.00
ALWAYS8255100.00

44 logic rising, falling; 45 1/1 assign falling = ~filter_out_d & filter_out_q; Tests: T27 T7 T16  46 1/1 assign rising = filter_out_d & ~filter_out_q; Tests: T27 T7 T16  47 48 logic cnt_en, cnt_eq_th; 49 logic [WkupCntWidth-1:0] cnt_d, cnt_q; 50 1/1 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; Tests: T63 T64 T65  51 52 1/1 assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i); Tests: T63 T64 T65  53 54 always_comb begin : p_mode 55 1/1 aon_wkup_pulse_o = 1'b0; Tests: T27 T7 T16  56 1/1 cnt_en = 1'b0; Tests: T27 T7 T16  57 1/1 if (wkup_en_i) begin Tests: T27 T7 T16  58 1/1 unique case (wkup_mode_i) Tests: T27 T7 T16  59 Negedge: begin 60 1/1 aon_wkup_pulse_o = falling; Tests: T16 T66 T67  61 end 62 Edge: begin 63 1/1 aon_wkup_pulse_o = rising | falling; Tests: T16 T66 T67  64 end 65 HighTimed: begin 66 0/1 ==> cnt_en = filter_out_d; 67 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 0/1 ==> cnt_en = ~filter_out_d; 71 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; 76 end 77 endcase 78 end MISSING_ELSE 79 end 80 81 always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 filter_out_q <= 1'b0; Tests: T1 T2 T3  84 1/1 cnt_q <= '0; Tests: T1 T2 T3  85 end else begin 86 1/1 filter_out_q <= filter_out_d; Tests: T1 T2 T3  87 1/1 cnt_q <= cnt_d; Tests: T1 T2 T3 

Cond Coverage for Module : pinmux_wkup
TotalCoveredPercent
Conditions131292.31
Logical131292.31
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----
-1--2-StatusTests
01CoveredT27,T7,T16
10CoveredT1,T2,T3
11CoveredT7,T16,T68

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT27,T7,T16
11CoveredT27,T7,T16

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----
-1-StatusTests
0CoveredT63,T64,T65
1CoveredT1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--
-1-StatusTests
0CoveredT63,T64,T65
1Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---
-1--2-StatusTests
00CoveredT16,T66,T67
01CoveredT16,T66,T67
10CoveredT16,T66,T67

Branch Coverage for Module : pinmux_wkup
Line No.TotalCoveredPercent
Branches 11 8 72.73
TERNARY 50 3 2 66.67
IF 57 6 4 66.67
IF 82 2 2 100.00


50 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; -1- -2- ==> ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T63,T64,T65


57 if (wkup_en_i) begin -1- 58 unique case (wkup_mode_i) -2- 59 Negedge: begin 60 aon_wkup_pulse_o = falling; ==> 61 end 62 Edge: begin 63 aon_wkup_pulse_o = rising | falling; ==> 64 end 65 HighTimed: begin 66 cnt_en = filter_out_d; ==> 67 aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 cnt_en = ~filter_out_d; ==> 71 aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; ==> 76 end 77 endcase 78 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 Negedge Covered T16,T66,T67
1 Edge Covered T16,T66,T67
1 HighTimed Not Covered
1 LowTimed Not Covered
1 default Covered T27,T7,T68
0 - Covered T27,T16,T63


82 if (!rst_ni) begin -1- 83 filter_out_q <= 1'b0; ==> 84 cnt_q <= '0; 85 end else begin 86 filter_out_q <= filter_out_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup
Line No.TotalCoveredPercent
TOTAL191052.63
CONT_ASSIGN45100.00
CONT_ASSIGN46100.00
CONT_ASSIGN5011100.00
CONT_ASSIGN5211100.00
ALWAYS5510330.00
ALWAYS8255100.00

44 logic rising, falling; 45 0/1 ==> assign falling = ~filter_out_d & filter_out_q; 46 0/1 ==> assign rising = filter_out_d & ~filter_out_q; 47 48 logic cnt_en, cnt_eq_th; 49 logic [WkupCntWidth-1:0] cnt_d, cnt_q; 50 1/1 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; Tests: T63 T64 T65  51 52 1/1 assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i); Tests: T63 T64 T65  53 54 always_comb begin : p_mode 55 1/1 aon_wkup_pulse_o = 1'b0; Tests: T63 T64 T65  56 1/1 cnt_en = 1'b0; Tests: T63 T64 T65  57 1/1 if (wkup_en_i) begin Tests: T63 T64 T65  58 0/1 ==> unique case (wkup_mode_i) 59 Negedge: begin 60 0/1 ==> aon_wkup_pulse_o = falling; 61 end 62 Edge: begin 63 0/1 ==> aon_wkup_pulse_o = rising | falling; 64 end 65 HighTimed: begin 66 0/1 ==> cnt_en = filter_out_d; 67 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 0/1 ==> cnt_en = ~filter_out_d; 71 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; 76 end 77 endcase 78 end MISSING_ELSE 79 end 80 81 always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 filter_out_q <= 1'b0; Tests: T1 T2 T3  84 1/1 cnt_q <= '0; Tests: T1 T2 T3  85 end else begin 86 1/1 filter_out_q <= filter_out_d; Tests: T1 T2 T3  87 1/1 cnt_q <= cnt_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup
TotalCoveredPercent
Conditions13538.46
Logical13538.46
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----
-1-StatusTests
0CoveredT63,T64,T65
1CoveredT1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--
-1-StatusTests
0CoveredT63,T64,T65
1Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup
Line No.TotalCoveredPercent
Branches 11 5 45.45
TERNARY 50 3 2 66.67
IF 57 6 1 16.67
IF 82 2 2 100.00


50 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; -1- -2- ==> ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T63,T64,T65


57 if (wkup_en_i) begin -1- 58 unique case (wkup_mode_i) -2- 59 Negedge: begin 60 aon_wkup_pulse_o = falling; ==> 61 end 62 Edge: begin 63 aon_wkup_pulse_o = rising | falling; ==> 64 end 65 HighTimed: begin 66 cnt_en = filter_out_d; ==> 67 aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 cnt_en = ~filter_out_d; ==> 71 aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; ==> 76 end 77 endcase 78 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 Negedge Not Covered
1 Edge Not Covered
1 HighTimed Not Covered
1 LowTimed Not Covered
1 default Not Covered
0 - Covered T63,T64,T65


82 if (!rst_ni) begin -1- 83 filter_out_q <= 1'b0; ==> 84 cnt_q <= '0; 85 end else begin 86 filter_out_q <= filter_out_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup
Line No.TotalCoveredPercent
TOTAL191052.63
CONT_ASSIGN45100.00
CONT_ASSIGN46100.00
CONT_ASSIGN5011100.00
CONT_ASSIGN5211100.00
ALWAYS5510330.00
ALWAYS8255100.00

44 logic rising, falling; 45 0/1 ==> assign falling = ~filter_out_d & filter_out_q; 46 0/1 ==> assign rising = filter_out_d & ~filter_out_q; 47 48 logic cnt_en, cnt_eq_th; 49 logic [WkupCntWidth-1:0] cnt_d, cnt_q; 50 1/1 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; Tests: T64  51 52 1/1 assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i); Tests: T64  53 54 always_comb begin : p_mode 55 1/1 aon_wkup_pulse_o = 1'b0; Tests: T64 T65  56 1/1 cnt_en = 1'b0; Tests: T64 T65  57 1/1 if (wkup_en_i) begin Tests: T64 T65  58 0/1 ==> unique case (wkup_mode_i) 59 Negedge: begin 60 0/1 ==> aon_wkup_pulse_o = falling; 61 end 62 Edge: begin 63 0/1 ==> aon_wkup_pulse_o = rising | falling; 64 end 65 HighTimed: begin 66 0/1 ==> cnt_en = filter_out_d; 67 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 0/1 ==> cnt_en = ~filter_out_d; 71 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; 76 end 77 endcase 78 end MISSING_ELSE 79 end 80 81 always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 filter_out_q <= 1'b0; Tests: T1 T2 T3  84 1/1 cnt_q <= '0; Tests: T1 T2 T3  85 end else begin 86 1/1 filter_out_q <= filter_out_d; Tests: T1 T2 T3  87 1/1 cnt_q <= cnt_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup
TotalCoveredPercent
Conditions13538.46
Logical13538.46
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----
-1-StatusTests
0CoveredT64
1CoveredT1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--
-1-StatusTests
0CoveredT64
1Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup
Line No.TotalCoveredPercent
Branches 11 5 45.45
TERNARY 50 3 2 66.67
IF 57 6 1 16.67
IF 82 2 2 100.00


50 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; -1- -2- ==> ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T64


57 if (wkup_en_i) begin -1- 58 unique case (wkup_mode_i) -2- 59 Negedge: begin 60 aon_wkup_pulse_o = falling; ==> 61 end 62 Edge: begin 63 aon_wkup_pulse_o = rising | falling; ==> 64 end 65 HighTimed: begin 66 cnt_en = filter_out_d; ==> 67 aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 cnt_en = ~filter_out_d; ==> 71 aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; ==> 76 end 77 endcase 78 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 Negedge Not Covered
1 Edge Not Covered
1 HighTimed Not Covered
1 LowTimed Not Covered
1 default Not Covered
0 - Covered T64,T65


82 if (!rst_ni) begin -1- 83 filter_out_q <= 1'b0; ==> 84 cnt_q <= '0; 85 end else begin 86 filter_out_q <= filter_out_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup
Line No.TotalCoveredPercent
TOTAL191052.63
CONT_ASSIGN45100.00
CONT_ASSIGN46100.00
CONT_ASSIGN5011100.00
CONT_ASSIGN5211100.00
ALWAYS5510330.00
ALWAYS8255100.00

44 logic rising, falling; 45 0/1 ==> assign falling = ~filter_out_d & filter_out_q; 46 0/1 ==> assign rising = filter_out_d & ~filter_out_q; 47 48 logic cnt_en, cnt_eq_th; 49 logic [WkupCntWidth-1:0] cnt_d, cnt_q; 50 1/1 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; Tests: T64  51 52 1/1 assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i); Tests: T64  53 54 always_comb begin : p_mode 55 1/1 aon_wkup_pulse_o = 1'b0; Tests: T64  56 1/1 cnt_en = 1'b0; Tests: T64  57 1/1 if (wkup_en_i) begin Tests: T64  58 0/1 ==> unique case (wkup_mode_i) 59 Negedge: begin 60 0/1 ==> aon_wkup_pulse_o = falling; 61 end 62 Edge: begin 63 0/1 ==> aon_wkup_pulse_o = rising | falling; 64 end 65 HighTimed: begin 66 0/1 ==> cnt_en = filter_out_d; 67 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 0/1 ==> cnt_en = ~filter_out_d; 71 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; 76 end 77 endcase 78 end MISSING_ELSE 79 end 80 81 always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 filter_out_q <= 1'b0; Tests: T1 T2 T3  84 1/1 cnt_q <= '0; Tests: T1 T2 T3  85 end else begin 86 1/1 filter_out_q <= filter_out_d; Tests: T1 T2 T3  87 1/1 cnt_q <= cnt_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup
TotalCoveredPercent
Conditions13538.46
Logical13538.46
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----
-1-StatusTests
0CoveredT64
1CoveredT1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--
-1-StatusTests
0CoveredT64
1Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup
Line No.TotalCoveredPercent
Branches 11 5 45.45
TERNARY 50 3 2 66.67
IF 57 6 1 16.67
IF 82 2 2 100.00


50 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; -1- -2- ==> ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T64


57 if (wkup_en_i) begin -1- 58 unique case (wkup_mode_i) -2- 59 Negedge: begin 60 aon_wkup_pulse_o = falling; ==> 61 end 62 Edge: begin 63 aon_wkup_pulse_o = rising | falling; ==> 64 end 65 HighTimed: begin 66 cnt_en = filter_out_d; ==> 67 aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 cnt_en = ~filter_out_d; ==> 71 aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; ==> 76 end 77 endcase 78 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 Negedge Not Covered
1 Edge Not Covered
1 HighTimed Not Covered
1 LowTimed Not Covered
1 default Not Covered
0 - Covered T64


82 if (!rst_ni) begin -1- 83 filter_out_q <= 1'b0; ==> 84 cnt_q <= '0; 85 end else begin 86 filter_out_q <= filter_out_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup
Line No.TotalCoveredPercent
TOTAL191263.16
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN5011100.00
CONT_ASSIGN5211100.00
ALWAYS5510330.00
ALWAYS8255100.00

44 logic rising, falling; 45 1/1 assign falling = ~filter_out_d & filter_out_q; Tests: T65  46 1/1 assign rising = filter_out_d & ~filter_out_q; Tests: T65  47 48 logic cnt_en, cnt_eq_th; 49 logic [WkupCntWidth-1:0] cnt_d, cnt_q; 50 1/1 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; Tests: T64 T65  51 52 1/1 assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i); Tests: T64 T65  53 54 always_comb begin : p_mode 55 1/1 aon_wkup_pulse_o = 1'b0; Tests: T64 T65  56 1/1 cnt_en = 1'b0; Tests: T64 T65  57 1/1 if (wkup_en_i) begin Tests: T64 T65  58 0/1 ==> unique case (wkup_mode_i) 59 Negedge: begin 60 0/1 ==> aon_wkup_pulse_o = falling; 61 end 62 Edge: begin 63 0/1 ==> aon_wkup_pulse_o = rising | falling; 64 end 65 HighTimed: begin 66 0/1 ==> cnt_en = filter_out_d; 67 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 0/1 ==> cnt_en = ~filter_out_d; 71 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; 76 end 77 endcase 78 end MISSING_ELSE 79 end 80 81 always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 filter_out_q <= 1'b0; Tests: T1 T2 T3  84 1/1 cnt_q <= '0; Tests: T1 T2 T3  85 end else begin 86 1/1 filter_out_q <= filter_out_d; Tests: T1 T2 T3  87 1/1 cnt_q <= cnt_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup
TotalCoveredPercent
Conditions13969.23
Logical13969.23
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----
-1--2-StatusTests
01CoveredT65
10CoveredT1,T2,T3
11CoveredT65

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT65
11CoveredT65

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----
-1-StatusTests
0CoveredT64,T65
1CoveredT1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--
-1-StatusTests
0CoveredT64,T65
1Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup
Line No.TotalCoveredPercent
Branches 11 5 45.45
TERNARY 50 3 2 66.67
IF 57 6 1 16.67
IF 82 2 2 100.00


50 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; -1- -2- ==> ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T64,T65


57 if (wkup_en_i) begin -1- 58 unique case (wkup_mode_i) -2- 59 Negedge: begin 60 aon_wkup_pulse_o = falling; ==> 61 end 62 Edge: begin 63 aon_wkup_pulse_o = rising | falling; ==> 64 end 65 HighTimed: begin 66 cnt_en = filter_out_d; ==> 67 aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 cnt_en = ~filter_out_d; ==> 71 aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; ==> 76 end 77 endcase 78 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 Negedge Not Covered
1 Edge Not Covered
1 HighTimed Not Covered
1 LowTimed Not Covered
1 default Not Covered
0 - Covered T64,T65


82 if (!rst_ni) begin -1- 83 filter_out_q <= 1'b0; ==> 84 cnt_q <= '0; 85 end else begin 86 filter_out_q <= filter_out_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup
Line No.TotalCoveredPercent
TOTAL191368.42
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN5011100.00
CONT_ASSIGN5211100.00
ALWAYS5510440.00
ALWAYS8255100.00

44 logic rising, falling; 45 1/1 assign falling = ~filter_out_d & filter_out_q; Tests: T29  46 1/1 assign rising = filter_out_d & ~filter_out_q; Tests: T29  47 48 logic cnt_en, cnt_eq_th; 49 logic [WkupCntWidth-1:0] cnt_d, cnt_q; 50 1/1 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; Tests: T64 T65  51 52 1/1 assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i); Tests: T64 T65  53 54 always_comb begin : p_mode 55 1/1 aon_wkup_pulse_o = 1'b0; Tests: T64 T29 T65  56 1/1 cnt_en = 1'b0; Tests: T64 T29 T65  57 1/1 if (wkup_en_i) begin Tests: T64 T29 T65  58 1/1 unique case (wkup_mode_i) Tests: T29  59 Negedge: begin 60 0/1 ==> aon_wkup_pulse_o = falling; 61 end 62 Edge: begin 63 0/1 ==> aon_wkup_pulse_o = rising | falling; 64 end 65 HighTimed: begin 66 0/1 ==> cnt_en = filter_out_d; 67 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 0/1 ==> cnt_en = ~filter_out_d; 71 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; 76 end 77 endcase 78 end MISSING_ELSE 79 end 80 81 always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 filter_out_q <= 1'b0; Tests: T1 T2 T3  84 1/1 cnt_q <= '0; Tests: T1 T2 T3  85 end else begin 86 1/1 filter_out_q <= filter_out_d; Tests: T1 T2 T3  87 1/1 cnt_q <= cnt_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup
TotalCoveredPercent
Conditions13861.54
Logical13861.54
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----
-1--2-StatusTests
01CoveredT29
10CoveredT1,T2,T3
11Not Covered

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT29
11CoveredT29

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----
-1-StatusTests
0CoveredT64,T65
1CoveredT1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--
-1-StatusTests
0CoveredT64,T65
1Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup
Line No.TotalCoveredPercent
Branches 11 6 54.55
TERNARY 50 3 2 66.67
IF 57 6 2 33.33
IF 82 2 2 100.00


50 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; -1- -2- ==> ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T64,T65


57 if (wkup_en_i) begin -1- 58 unique case (wkup_mode_i) -2- 59 Negedge: begin 60 aon_wkup_pulse_o = falling; ==> 61 end 62 Edge: begin 63 aon_wkup_pulse_o = rising | falling; ==> 64 end 65 HighTimed: begin 66 cnt_en = filter_out_d; ==> 67 aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 cnt_en = ~filter_out_d; ==> 71 aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; ==> 76 end 77 endcase 78 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 Negedge Not Covered
1 Edge Not Covered
1 HighTimed Not Covered
1 LowTimed Not Covered
1 default Covered T29
0 - Covered T64,T29,T65


82 if (!rst_ni) begin -1- 83 filter_out_q <= 1'b0; ==> 84 cnt_q <= '0; 85 end else begin 86 filter_out_q <= filter_out_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup
Line No.TotalCoveredPercent
TOTAL191368.42
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN5011100.00
CONT_ASSIGN5211100.00
ALWAYS5510440.00
ALWAYS8255100.00

44 logic rising, falling; 45 1/1 assign falling = ~filter_out_d & filter_out_q; Tests: T27 T64  46 1/1 assign rising = filter_out_d & ~filter_out_q; Tests: T27 T64  47 48 logic cnt_en, cnt_eq_th; 49 logic [WkupCntWidth-1:0] cnt_d, cnt_q; 50 1/1 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; Tests: T64  51 52 1/1 assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i); Tests: T64  53 54 always_comb begin : p_mode 55 1/1 aon_wkup_pulse_o = 1'b0; Tests: T27 T64  56 1/1 cnt_en = 1'b0; Tests: T27 T64  57 1/1 if (wkup_en_i) begin Tests: T27 T64  58 1/1 unique case (wkup_mode_i) Tests: T27  59 Negedge: begin 60 0/1 ==> aon_wkup_pulse_o = falling; 61 end 62 Edge: begin 63 0/1 ==> aon_wkup_pulse_o = rising | falling; 64 end 65 HighTimed: begin 66 0/1 ==> cnt_en = filter_out_d; 67 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 0/1 ==> cnt_en = ~filter_out_d; 71 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; 76 end 77 endcase 78 end MISSING_ELSE 79 end 80 81 always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 filter_out_q <= 1'b0; Tests: T1 T2 T3  84 1/1 cnt_q <= '0; Tests: T1 T2 T3  85 end else begin 86 1/1 filter_out_q <= filter_out_d; Tests: T1 T2 T3  87 1/1 cnt_q <= cnt_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup
TotalCoveredPercent
Conditions13969.23
Logical13969.23
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----
-1--2-StatusTests
01CoveredT27,T64
10CoveredT1,T2,T3
11CoveredT64

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT27,T64
11CoveredT27,T64

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----
-1-StatusTests
0CoveredT64
1CoveredT1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--
-1-StatusTests
0CoveredT64
1Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup
Line No.TotalCoveredPercent
Branches 11 6 54.55
TERNARY 50 3 2 66.67
IF 57 6 2 33.33
IF 82 2 2 100.00


50 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; -1- -2- ==> ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T64


57 if (wkup_en_i) begin -1- 58 unique case (wkup_mode_i) -2- 59 Negedge: begin 60 aon_wkup_pulse_o = falling; ==> 61 end 62 Edge: begin 63 aon_wkup_pulse_o = rising | falling; ==> 64 end 65 HighTimed: begin 66 cnt_en = filter_out_d; ==> 67 aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 cnt_en = ~filter_out_d; ==> 71 aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; ==> 76 end 77 endcase 78 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 Negedge Not Covered
1 Edge Not Covered
1 HighTimed Not Covered
1 LowTimed Not Covered
1 default Covered T27
0 - Covered T27,T64


82 if (!rst_ni) begin -1- 83 filter_out_q <= 1'b0; ==> 84 cnt_q <= '0; 85 end else begin 86 filter_out_q <= filter_out_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup
Line No.TotalCoveredPercent
TOTAL191368.42
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN5011100.00
CONT_ASSIGN5211100.00
ALWAYS5510440.00
ALWAYS8255100.00

44 logic rising, falling; 45 1/1 assign falling = ~filter_out_d & filter_out_q; Tests: T68 T69 T70  46 1/1 assign rising = filter_out_d & ~filter_out_q; Tests: T68 T69 T70  47 48 logic cnt_en, cnt_eq_th; 49 logic [WkupCntWidth-1:0] cnt_d, cnt_q; 50 1/1 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; Tests: T64 T65  51 52 1/1 assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i); Tests: T64 T65  53 54 always_comb begin : p_mode 55 1/1 aon_wkup_pulse_o = 1'b0; Tests: T68 T69 T70  56 1/1 cnt_en = 1'b0; Tests: T68 T69 T70  57 1/1 if (wkup_en_i) begin Tests: T68 T69 T70  58 1/1 unique case (wkup_mode_i) Tests: T68 T69 T70  59 Negedge: begin 60 0/1 ==> aon_wkup_pulse_o = falling; 61 end 62 Edge: begin 63 0/1 ==> aon_wkup_pulse_o = rising | falling; 64 end 65 HighTimed: begin 66 0/1 ==> cnt_en = filter_out_d; 67 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 0/1 ==> cnt_en = ~filter_out_d; 71 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; 76 end 77 endcase 78 end MISSING_ELSE 79 end 80 81 always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 filter_out_q <= 1'b0; Tests: T1 T2 T3  84 1/1 cnt_q <= '0; Tests: T1 T2 T3  85 end else begin 86 1/1 filter_out_q <= filter_out_d; Tests: T1 T2 T3  87 1/1 cnt_q <= cnt_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup
TotalCoveredPercent
Conditions13969.23
Logical13969.23
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----
-1--2-StatusTests
01CoveredT68,T69,T70
10CoveredT1,T2,T3
11CoveredT68,T69,T70

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT68,T69,T70
11CoveredT68,T69,T70

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----
-1-StatusTests
0CoveredT64,T65
1CoveredT1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--
-1-StatusTests
0CoveredT64,T65
1Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup
Line No.TotalCoveredPercent
Branches 11 6 54.55
TERNARY 50 3 2 66.67
IF 57 6 2 33.33
IF 82 2 2 100.00


50 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; -1- -2- ==> ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T64,T65


57 if (wkup_en_i) begin -1- 58 unique case (wkup_mode_i) -2- 59 Negedge: begin 60 aon_wkup_pulse_o = falling; ==> 61 end 62 Edge: begin 63 aon_wkup_pulse_o = rising | falling; ==> 64 end 65 HighTimed: begin 66 cnt_en = filter_out_d; ==> 67 aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 cnt_en = ~filter_out_d; ==> 71 aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; ==> 76 end 77 endcase 78 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 Negedge Not Covered
1 Edge Not Covered
1 HighTimed Not Covered
1 LowTimed Not Covered
1 default Covered T68,T69,T70
0 - Covered T69,T64,T65


82 if (!rst_ni) begin -1- 83 filter_out_q <= 1'b0; ==> 84 cnt_q <= '0; 85 end else begin 86 filter_out_q <= filter_out_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup
Line No.TotalCoveredPercent
TOTAL191578.95
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN5011100.00
CONT_ASSIGN5211100.00
ALWAYS5510660.00
ALWAYS8255100.00

44 logic rising, falling; 45 1/1 assign falling = ~filter_out_d & filter_out_q; Tests: T7 T16 T71  46 1/1 assign rising = filter_out_d & ~filter_out_q; Tests: T7 T16 T71  47 48 logic cnt_en, cnt_eq_th; 49 logic [WkupCntWidth-1:0] cnt_d, cnt_q; 50 1/1 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; Tests: T64 T65  51 52 1/1 assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i); Tests: T64 T65  53 54 always_comb begin : p_mode 55 1/1 aon_wkup_pulse_o = 1'b0; Tests: T7 T16 T64  56 1/1 cnt_en = 1'b0; Tests: T7 T16 T64  57 1/1 if (wkup_en_i) begin Tests: T7 T16 T64  58 1/1 unique case (wkup_mode_i) Tests: T7 T16 T71  59 Negedge: begin 60 1/1 aon_wkup_pulse_o = falling; Tests: T16 T66 T67  61 end 62 Edge: begin 63 1/1 aon_wkup_pulse_o = rising | falling; Tests: T16 T66 T67  64 end 65 HighTimed: begin 66 0/1 ==> cnt_en = filter_out_d; 67 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 0/1 ==> cnt_en = ~filter_out_d; 71 0/1 ==> aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; 76 end 77 endcase 78 end MISSING_ELSE 79 end 80 81 always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 filter_out_q <= 1'b0; Tests: T1 T2 T3  84 1/1 cnt_q <= '0; Tests: T1 T2 T3  85 end else begin 86 1/1 filter_out_q <= filter_out_d; Tests: T1 T2 T3  87 1/1 cnt_q <= cnt_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup
TotalCoveredPercent
Conditions131292.31
Logical131292.31
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----
-1--2-StatusTests
01CoveredT7,T16,T71
10CoveredT1,T2,T3
11CoveredT7,T16,T71

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T16,T71
11CoveredT7,T16,T71

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----
-1-StatusTests
0CoveredT64,T65
1CoveredT1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--
-1-StatusTests
0CoveredT64,T65
1Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---
-1--2-StatusTests
00CoveredT16,T66,T67
01CoveredT16,T66,T67
10CoveredT16,T66,T67

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup
Line No.TotalCoveredPercent
Branches 11 8 72.73
TERNARY 50 3 2 66.67
IF 57 6 4 66.67
IF 82 2 2 100.00


50 assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; -1- -2- ==> ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T64,T65


57 if (wkup_en_i) begin -1- 58 unique case (wkup_mode_i) -2- 59 Negedge: begin 60 aon_wkup_pulse_o = falling; ==> 61 end 62 Edge: begin 63 aon_wkup_pulse_o = rising | falling; ==> 64 end 65 HighTimed: begin 66 cnt_en = filter_out_d; ==> 67 aon_wkup_pulse_o = cnt_eq_th; 68 end 69 LowTimed: begin 70 cnt_en = ~filter_out_d; ==> 71 aon_wkup_pulse_o = cnt_eq_th; 72 end 73 // Default to rising 74 default: begin 75 aon_wkup_pulse_o = rising; ==> 76 end 77 endcase 78 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 Negedge Covered T16,T66,T67
1 Edge Covered T16,T66,T67
1 HighTimed Not Covered
1 LowTimed Not Covered
1 default Covered T7,T71,T72
0 - Covered T16,T64,T66


82 if (!rst_ni) begin -1- 83 filter_out_q <= 1'b0; ==> 84 cnt_q <= '0; 85 end else begin 86 filter_out_q <= filter_out_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%