Unified Coverage Report :: Module :: clk_ctrl_and_main_pd_sva_if

Module : clk_ctrl_and_main_pd_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_top_earlgrey_sva_0.1/clk_ctrl_and_main_pd_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.clk_ctrl_and_main_pd_sva_if	100.00			100.00

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Module Instance : tb.dut.top_earlgrey.clk_ctrl_and_main_pd_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.82	92.11		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

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Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : clk_ctrl_and_main_pd_sva_if

	Total	Covered	Percent
Totals	14	14	100.00
Total Bits	28	28	100.00
Total Bits 0->1	14	14	100.00
Total Bits 1->0	14	14	100.00

Ports	14	14	100.00
Port Bits	28	28	100.00
Port Bits 0->1	14	14	100.00
Port Bits 1->0	14	14	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_slow_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_slow_ni	Yes	Yes	T42,T37,T43	Yes	T1,T2,T3	INPUT
por_d0_ni	Yes	Yes	T27,T42,T39	Yes	T1,T2,T3	INPUT
core_clk_en	Yes	Yes	T8,T27,T7	Yes	T1,T2,T3	INPUT
core_clk_val	Yes	Yes	T8,T27,T7	Yes	T1,T2,T3	INPUT
clk_core_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
io_clk_en	Yes	Yes	T8,T27,T7	Yes	T1,T2,T3	INPUT
io_clk_val	Yes	Yes	T8,T27,T7	Yes	T1,T2,T3	INPUT
clk_io_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
usb_clk_en	Yes	Yes	T8,T27,T7	Yes	T1,T2,T3	INPUT
usb_clk_val	Yes	Yes	T8,T27,T7	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
main_pd_n	Yes	Yes	T27,T39,T155	Yes	T27,T39,T155	INPUT
main_pok	Yes	Yes	T27,T42,T39	Yes	T1,T2,T3	INPUT