Unified Coverage Report :: Module :: rstmgr

Module : rstmgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rstmgr_aon	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rstmgr_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.82	92.11		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : rstmgr

	Total	Covered	Percent
Totals	59	59	100.00
Total Bits	390	390	100.00
Total Bits 0->1	195	195	100.00
Total Bits 1->0	195	195	100.00

Ports	59	59	100.00
Port Bits	390	390	100.00
Port Bits 0->1	195	195	100.00
Port Bits 1->0	195	195	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T48,T49,T50	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_io_div4_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_io_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_io_div2_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_por_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_por_ni	Yes	Yes	T42,T37,T43	Yes	T1,T2,T3	INPUT
por_n_i[1:0]	Yes	Yes	T42,T37,T43	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T102,*T103,*T104	Yes	T102,T103,T104	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[21:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	INPUT
tl_i.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_o.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_error	Yes	Yes	T103,T104,T105	Yes	T102,T103,T104	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T27,T48,T49	Yes	T2,T3,T4	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T27,T48,T49	Yes	T2,T3,T4	OUTPUT
tl_o.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T64,*T65,*T104	Yes	T64,T65,T102	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T103,T104,T105	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T87,T106,T107	Yes	T87,T106,T107	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T106,T107,T108	Yes	T106,T107,T108	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T106,T107,T108	Yes	T106,T107,T108	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T49,T87,T106	Yes	T49,T87,T106	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T106,T107,T196	Yes	T106,T107,T196	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T106,T107,T196	Yes	T106,T107,T196	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T87,T106,T107	Yes	T87,T106,T107	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T49,T87,T106	Yes	T49,T87,T106	OUTPUT
pwr_i.reset_cause[1:0]	Yes	Yes	T1,T2,T3	Yes	T8,T27,T7	INPUT
pwr_i.rstreqs[4:0]	Yes	Yes	T83,T84,T137	Yes	T83,T84,T137	INPUT
pwr_i.rst_sys_req[1:0]	Yes	Yes	T1,T2,T3	Yes	T48,T49,T50	INPUT
pwr_i.rst_lc_req[1:0]	Yes	Yes	T1,T2,T3	Yes	T48,T49,T50	INPUT
pwr_o.rst_sys_src_n[1:0]	Yes	Yes	T48,T49,T50	Yes	T1,T2,T3	OUTPUT
pwr_o.rst_lc_src_n[1:0]	Yes	Yes	T48,T49,T50	Yes	T1,T2,T3	OUTPUT
sw_rst_req_o[3:0]	Yes	Yes	T236,T253,T208	Yes	T236,T253,T208	OUTPUT
alert_dump_i.class_esc_cnt[3:0][31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_dump_i.class_accum_cnt[3:0][15:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_dump_i.loc_alert_cause[6:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_dump_i.alert_cause[64:0]	Unreachable	Unreachable		Unreachable		INPUT
cpu_dump_i.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		INPUT
cpu_dump_i.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		INPUT
cpu_dump_i.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		INPUT
cpu_dump_i.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		INPUT
cpu_dump_i.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		INPUT
cpu_dump_i.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		INPUT
cpu_dump_i.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		INPUT
cpu_dump_i.prev_valid	Unreachable	Unreachable		Unreachable		INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
resets_o.rst_i2c2_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_i2c1_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_i2c0_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_usb_aon_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_usb_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_spi_host1_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_spi_host0_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_spi_device_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_sys_io_div4_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_sys_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_lc_usb_n[1:0]	Yes	Yes	T48,T49,T50	Yes	T1,T2,T3	OUTPUT
resets_o.rst_lc_io_div4_n[1:0]	Yes	Yes	T48,T49,T50	Yes	T1,T2,T3	OUTPUT
resets_o.rst_lc_io_div4_shadowed_n[1:0]	Yes	Yes	T48,T49,T50	Yes	T1,T2,T3	OUTPUT
resets_o.rst_lc_io_div2_n[1:0]	Yes	Yes	T48,T49,T50	Yes	T1,T2,T3	OUTPUT
resets_o.rst_lc_io_n[1:0]	Yes	Yes	T48,T49,T50	Yes	T1,T2,T3	OUTPUT
resets_o.rst_lc_aon_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_lc_n[1:0]	Yes	Yes	T48,T49,T50	Yes	T1,T2,T3	OUTPUT
resets_o.rst_lc_shadowed_n[1:0]	Yes	Yes	T48,T49,T50	Yes	T1,T2,T3	OUTPUT
resets_o.rst_por_usb_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_por_io_div4_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_por_io_div2_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_por_io_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_por_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_por_aon_n[1:0]	Yes	Yes	T42,T37,T43	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range