Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	549436499	64988084	0	0
DepthKnown_A	549436499	549329916	0	0
RvalidKnown_A	549436499	549329916	0	0
WreadyKnown_A	549436499	549329916	0	0
gen_passthru_fifo.paramCheckPass	1030	1030	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549436499	64988084	0	0
T1	42280	3485	0	0
T2	61148	5728	0	0
T3	65177	6248	0	0
T4	91950	11136	0	0
T5	115823	76243	0	0
T6	104855	9176	0	0
T8	105965	11591	0	0
T9	90200	10111	0	0
T27	149974	17666	0	0
T38	61154	6293	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549436499	549329916	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549436499	549329916	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549436499	549329916	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T27	1	1	0	0
T38	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         0/1     ==>      assign wready_o = rready_i;
49         0/1     ==>      assign full_o = rready_i;
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	549436499	50372258	0	0
DepthKnown_A	549436499	549329916	0	0
RvalidKnown_A	549436499	549329916	0	0
WreadyKnown_A	549436499	549329916	0	0
gen_passthru_fifo.paramCheckPass	1030	1030	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549436499	50372258	0	0
T1	42280	1880	0	0
T2	61148	4060	0	0
T3	65177	4578	0	0
T4	91950	8581	0	0
T5	115823	37720	0	0
T6	104855	6443	0	0
T8	105965	9051	0	0
T9	90200	7649	0	0
T27	149974	12579	0	0
T38	61154	4198	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549436499	549329916	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549436499	549329916	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549436499	549329916	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T27	1	1	0	0
T38	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	549436499	45136430	0	0
DepthKnown_A	549436499	549329916	0	0
RvalidKnown_A	549436499	549329916	0	0
WreadyKnown_A	549436499	549329916	0	0
gen_passthru_fifo.paramCheckPass	1030	1030	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549436499	45136430	0	0
T1	42280	461	0	0
T2	61148	3317	0	0
T3	65177	3693	0	0
T4	91950	7349	0	0
T5	115823	7542	0	0
T6	104855	4518	0	0
T8	105965	9111	0	0
T9	90200	4704	0	0
T27	149974	8914	0	0
T38	61154	3098	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549436499	549329916	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549436499	549329916	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549436499	549329916	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T27	1	1	0	0
T38	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T41 T64 T65 
49         1/1              assign full_o = rready_i;
           Tests:       T41 T64 T65 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	549436499	38034328	0	0
DepthKnown_A	549436499	549329916	0	0
RvalidKnown_A	549436499	549329916	0	0
WreadyKnown_A	549436499	549329916	0	0
gen_passthru_fifo.paramCheckPass	1030	1030	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549436499	38034328	0	0
T1	42280	353	0	0
T2	61148	3203	0	0
T3	65177	3579	0	0
T4	91950	7174	0	0
T5	115823	6881	0	0
T6	104855	4346	0	0
T8	105965	8656	0	0
T9	90200	4565	0	0
T27	149974	8647	0	0
T38	61154	2972	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549436499	549329916	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549436499	549329916	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549436499	549329916	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T27	1	1	0	0
T38	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	645547705	101595	0	0
DepthKnown_A	645547705	645425184	0	0
RvalidKnown_A	645547705	645425184	0	0
WreadyKnown_A	645547705	645425184	0	0
gen_passthru_fifo.paramCheckPass	2941	2941	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	101595	0	0
T1	42280	8	0	0
T2	61148	13	0	0
T3	65177	13	0	0
T4	91950	24	0	0
T5	115823	34	0	0
T6	104855	23	0	0
T8	105965	208	0	0
T9	90200	13	0	0
T27	149974	35	0	0
T38	61154	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	645425184	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	645425184	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	645425184	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2941	2941	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T27	1	1	0	0
T38	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	645547705	104084	0	0
DepthKnown_A	645547705	645425184	0	0
RvalidKnown_A	645547705	645425184	0	0
WreadyKnown_A	645547705	645425184	0	0
gen_passthru_fifo.paramCheckPass	2941	2941	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	104084	0	0
T1	42280	8	0	0
T2	61148	13	0	0
T3	65177	13	0	0
T4	91950	24	0	0
T5	115823	34	0	0
T6	104855	23	0	0
T8	105965	208	0	0
T9	90200	13	0	0
T27	149974	35	0	0
T38	61154	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	645425184	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	645425184	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	645425184	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2941	2941	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T27	1	1	0	0
T38	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	645547705	52734	0	0
DepthKnown_A	645547705	645425184	0	0
RvalidKnown_A	645547705	645425184	0	0
WreadyKnown_A	645547705	645425184	0	0
gen_passthru_fifo.paramCheckPass	2941	2941	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	52734	0	0
T1	42280	8	0	0
T2	61148	12	0	0
T3	65177	12	0	0
T4	91950	23	0	0
T5	115823	31	0	0
T6	104855	20	0	0
T8	105965	205	0	0
T9	90200	12	0	0
T27	149974	31	0	0
T38	61154	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	645425184	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	645425184	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	645425184	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2941	2941	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T27	1	1	0	0
T38	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	645547705	52734	0	0
DepthKnown_A	645547705	645425184	0	0
RvalidKnown_A	645547705	645425184	0	0
WreadyKnown_A	645547705	645425184	0	0
gen_passthru_fifo.paramCheckPass	2941	2941	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	52734	0	0
T1	42280	8	0	0
T2	61148	12	0	0
T3	65177	12	0	0
T4	91950	23	0	0
T5	115823	31	0	0
T6	104855	20	0	0
T8	105965	205	0	0
T9	90200	12	0	0
T27	149974	31	0	0
T38	61154	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	645425184	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	645425184	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	645425184	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2941	2941	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T27	1	1	0	0
T38	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T2 T3 T4 
49         1/1              assign full_o = rready_i;
           Tests:       T2 T3 T4 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	645547705	48861	0	0
DepthKnown_A	645547705	645425184	0	0
RvalidKnown_A	645547705	645425184	0	0
WreadyKnown_A	645547705	645425184	0	0
gen_passthru_fifo.paramCheckPass	2941	2941	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	48861	0	0
T2	61148	1	0	0
T3	65177	1	0	0
T4	91950	1	0	0
T5	115823	3	0	0
T6	104855	3	0	0
T8	105965	3	0	0
T9	90200	1	0	0
T10	145349	1	0	0
T27	149974	4	0	0
T38	61154	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	645425184	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	645425184	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	645425184	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2941	2941	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T27	1	1	0	0
T38	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T2 T3 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	645547705	51350	0	0
DepthKnown_A	645547705	645425184	0	0
RvalidKnown_A	645547705	645425184	0	0
WreadyKnown_A	645547705	645425184	0	0
gen_passthru_fifo.paramCheckPass	2941	2941	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	51350	0	0
T2	61148	1	0	0
T3	65177	1	0	0
T4	91950	1	0	0
T5	115823	3	0	0
T6	104855	3	0	0
T8	105965	3	0	0
T9	90200	1	0	0
T10	145349	1	0	0
T27	149974	4	0	0
T38	61154	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	645425184	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	645425184	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645547705	645425184	0	0
T1	42280	42218	0	0
T2	61148	61086	0	0
T3	65177	65115	0	0
T4	91950	91888	0	0
T5	115823	115768	0	0
T6	104855	104797	0	0
T8	105965	105907	0	0
T9	90200	90142	0	0
T27	149974	149862	0	0
T38	61154	61092	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2941	2941	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T27	1	1	0	0
T38	1	1	0	0