Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_recov_alert_val_8.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
87 // If both try to set/clr at the same bit pos, SW wins.
88 1/1 assign wr_en = we | de;
Tests: T165 T167 T68
89 if (Mubi) begin : gen_mubi
90 if (DW == 4) begin : gen_mubi4
91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
92 (we ? prim_mubi_pkg::mubi4_t'(~wd) :
93 prim_mubi_pkg::MuBi4True));
94 end else if (DW == 8) begin : gen_mubi8
95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
96 (we ? prim_mubi_pkg::mubi8_t'(~wd) :
97 prim_mubi_pkg::MuBi8True));
98 end else if (DW == 12) begin : gen_mubi12
99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
100 (we ? prim_mubi_pkg::mubi12_t'(~wd) :
101 prim_mubi_pkg::MuBi12True));
102 end else if (DW == 16) begin : gen_mubi16
103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
104 (we ? prim_mubi_pkg::mubi16_t'(~wd) :
105 prim_mubi_pkg::MuBi16True));
106 end else begin : gen_invalid_mubi
107 $error("%m: Invalid width for MuBi");
108 end
109 end else begin : gen_non_mubi
110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1);
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_recov_alert_val_8.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T165,T141,T170 |
| 1 | 0 | Covered | T165,T167,T68 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T165,T141,T170 |
| 1 | 1 | Covered | T165,T141,T170 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T165,T141,T170 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T165,T167,T68 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_recov_alert_val_9.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
87 // If both try to set/clr at the same bit pos, SW wins.
88 1/1 assign wr_en = we | de;
Tests: T165 T167 T68
89 if (Mubi) begin : gen_mubi
90 if (DW == 4) begin : gen_mubi4
91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
92 (we ? prim_mubi_pkg::mubi4_t'(~wd) :
93 prim_mubi_pkg::MuBi4True));
94 end else if (DW == 8) begin : gen_mubi8
95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
96 (we ? prim_mubi_pkg::mubi8_t'(~wd) :
97 prim_mubi_pkg::MuBi8True));
98 end else if (DW == 12) begin : gen_mubi12
99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
100 (we ? prim_mubi_pkg::mubi12_t'(~wd) :
101 prim_mubi_pkg::MuBi12True));
102 end else if (DW == 16) begin : gen_mubi16
103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
104 (we ? prim_mubi_pkg::mubi16_t'(~wd) :
105 prim_mubi_pkg::MuBi16True));
106 end else begin : gen_invalid_mubi
107 $error("%m: Invalid width for MuBi");
108 end
109 end else begin : gen_non_mubi
110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1);
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_recov_alert_val_9.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T165,T170,T171 |
| 1 | 0 | Covered | T165,T167,T68 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T165,T170,T171 |
| 1 | 1 | Covered | T165,T170,T171 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T165,T170,T171 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T165,T167,T68 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_recov_alert_val_10.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
87 // If both try to set/clr at the same bit pos, SW wins.
88 1/1 assign wr_en = we | de;
Tests: T165 T167 T68
89 if (Mubi) begin : gen_mubi
90 if (DW == 4) begin : gen_mubi4
91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
92 (we ? prim_mubi_pkg::mubi4_t'(~wd) :
93 prim_mubi_pkg::MuBi4True));
94 end else if (DW == 8) begin : gen_mubi8
95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
96 (we ? prim_mubi_pkg::mubi8_t'(~wd) :
97 prim_mubi_pkg::MuBi8True));
98 end else if (DW == 12) begin : gen_mubi12
99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
100 (we ? prim_mubi_pkg::mubi12_t'(~wd) :
101 prim_mubi_pkg::MuBi12True));
102 end else if (DW == 16) begin : gen_mubi16
103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
104 (we ? prim_mubi_pkg::mubi16_t'(~wd) :
105 prim_mubi_pkg::MuBi16True));
106 end else begin : gen_invalid_mubi
107 $error("%m: Invalid width for MuBi");
108 end
109 end else begin : gen_non_mubi
110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1);
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_recov_alert_val_10.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T165,T170,T171 |
| 1 | 0 | Covered | T165,T167,T68 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T165,T170,T171 |
| 1 | 1 | Covered | T165,T170,T171 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T165,T170,T171 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T165,T167,T68 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_fatal_alert_val_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 0 | 0.00 |
| CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 0/1 ==> assign wr_data = d;
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_fatal_alert_val_1.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 1 | 50.00 |
| CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 1/1 assign wr_en = de;
Tests: T167 T168 T169
44 0/1 ==> assign wr_data = d;
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_fatal_alert_val_2.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 1 | 50.00 |
| CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 1/1 assign wr_en = de;
Tests: T172 T173
44 0/1 ==> assign wr_data = d;
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_fatal_alert_val_3.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 0 | 0.00 |
| CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 0/1 ==> assign wr_data = d;
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_fatal_alert_val_4.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 1 | 50.00 |
| CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 1/1 assign wr_en = de;
Tests: T167 T168 T169
44 0/1 ==> assign wr_data = d;
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_fatal_alert_val_5.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 0 | 0.00 |
| CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 0/1 ==> assign wr_data = d;
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_fatal_alert_val_6.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 1 | 50.00 |
| CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 1/1 assign wr_en = de;
Tests: T172 T173
44 0/1 ==> assign wr_data = d;
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_fatal_alert_val_7.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 0 | 0.00 |
| CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 0/1 ==> assign wr_data = d;
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_fatal_alert_val_8.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 0 | 0.00 |
| CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 0/1 ==> assign wr_data = d;
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_fatal_alert_val_9.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 0 | 0.00 |
| CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 0/1 ==> assign wr_data = d;
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;