Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.82	92.11		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.82	92.11		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.82	92.11		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.82	92.11		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T32,T126,T131	Yes	T32,T126,T131	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T32,T126,T131	Yes	T32,T126,T131	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T102,*T103,*T104	Yes	T102,T103,T104	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	INPUT
tl_i.a_valid	Yes	Yes	T32,T126,T131	Yes	T32,T126,T131	INPUT
tl_o.a_ready	Yes	Yes	T32,T126,T131	Yes	T32,T126,T131	OUTPUT
tl_o.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T32,T126,T131	Yes	T32,T126,T131	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T32,T126,T131	Yes	T32,T126,T131	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T32,T126,T131	Yes	T32,T126,T131	OUTPUT
tl_o.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T271,*T273,*T104	Yes	T271,T273,T102	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T32,*T126,*T131	Yes	T32,T126,T131	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T32,T126,T131	Yes	T32,T126,T131	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T198,T87,T106	Yes	T198,T87,T106	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T106,T107,T196	Yes	T106,T107,T196	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T106,T107,T196	Yes	T106,T107,T196	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T198,T87,T106	Yes	T198,T87,T106	OUTPUT
cio_rx_i	Yes	Yes	T48,T49,T32	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T32,T126,T131	Yes	T32,T126,T131	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T32,T126,T131	Yes	T32,T126,T131	OUTPUT
intr_tx_empty_o	Yes	Yes	T32,T126,T131	Yes	T32,T126,T131	OUTPUT
intr_rx_watermark_o	Yes	Yes	T32,T126,T131	Yes	T32,T126,T131	OUTPUT
intr_tx_done_o	Yes	Yes	T32,T126,T131	Yes	T32,T126,T131	OUTPUT
intr_rx_overflow_o	Yes	Yes	T32,T126,T131	Yes	T32,T126,T131	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T333,T338,T339	Yes	T333,T338,T339	OUTPUT
intr_rx_break_err_o	Yes	Yes	T333,T338,T339	Yes	T333,T338,T339	OUTPUT
intr_rx_timeout_o	Yes	Yes	T333,T338,T339	Yes	T333,T338,T339	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T333,T338,T339	Yes	T333,T338,T339	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T126,T36,T262	Yes	T126,T36,T262	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T126,T36,T262	Yes	T126,T36,T262	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T102,*T103,*T104	Yes	T102,T103,T104	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	INPUT
tl_i.a_valid	Yes	Yes	T126,T36,T198	Yes	T126,T36,T198	INPUT
tl_o.a_ready	Yes	Yes	T126,T36,T198	Yes	T126,T36,T198	OUTPUT
tl_o.d_error	Yes	Yes	T104,T105,T162	Yes	T103,T104,T105	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T126,T36,T333	Yes	T126,T36,T333	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T126,T36,T198	Yes	T126,T36,T198	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T126,T36,T198	Yes	T126,T36,T198	OUTPUT
tl_o.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T271,*T273,*T104	Yes	T271,T273,T102	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T126,*T36,*T333	Yes	T126,T36,T333	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T126,T36,T198	Yes	T126,T36,T198	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T198,T87,T106	Yes	T198,T87,T106	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T106,T107,T196	Yes	T106,T107,T196	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T106,T107,T196	Yes	T106,T107,T196	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T198,T87,T106	Yes	T198,T87,T106	OUTPUT
cio_rx_i	Yes	Yes	T48,T49,T50	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T126,T36,T60	Yes	T126,T36,T60	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T126,T36,T333	Yes	T126,T36,T333	OUTPUT
intr_tx_empty_o	Yes	Yes	T126,T36,T333	Yes	T126,T36,T333	OUTPUT
intr_rx_watermark_o	Yes	Yes	T126,T36,T333	Yes	T126,T36,T333	OUTPUT
intr_tx_done_o	Yes	Yes	T126,T36,T333	Yes	T126,T36,T333	OUTPUT
intr_rx_overflow_o	Yes	Yes	T126,T36,T333	Yes	T126,T36,T333	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T333,T338,T339	Yes	T333,T338,T339	OUTPUT
intr_rx_break_err_o	Yes	Yes	T333,T338,T339	Yes	T333,T338,T339	OUTPUT
intr_rx_timeout_o	Yes	Yes	T333,T338,T339	Yes	T333,T338,T339	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T333,T338,T339	Yes	T333,T338,T339	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T131,T333,T15	Yes	T131,T333,T15	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T131,T333,T15	Yes	T131,T333,T15	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T102,*T103,*T104	Yes	T102,T103,T104	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	INPUT
tl_i.a_valid	Yes	Yes	T131,T198,T87	Yes	T131,T198,T87	INPUT
tl_o.a_ready	Yes	Yes	T131,T198,T87	Yes	T131,T198,T87	OUTPUT
tl_o.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T131,T333,T15	Yes	T131,T333,T15	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T131,T198,T333	Yes	T131,T198,T87	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T131,T198,T333	Yes	T131,T198,T87	OUTPUT
tl_o.d_sink	Yes	Yes	T102,T104,T162	Yes	T102,T104,T162	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T104,*T162,*T163	Yes	T102,T104,T162	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T104,T105	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T131,*T333,*T15	Yes	T131,T333,T15	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T131,T198,T87	Yes	T131,T198,T87	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T198,T87,T106	Yes	T198,T87,T106	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T106,T107,T196	Yes	T106,T107,T196	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T106,T107,T196	Yes	T106,T107,T196	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T198,T87,T106	Yes	T198,T87,T106	OUTPUT
cio_rx_i	Yes	Yes	T131,T132,T133	Yes	T8,T12,T131	INPUT
cio_tx_o	Yes	Yes	T131,T132,T133	Yes	T131,T132,T133	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T131,T333,T132	Yes	T131,T333,T132	OUTPUT
intr_tx_empty_o	Yes	Yes	T131,T333,T132	Yes	T131,T333,T132	OUTPUT
intr_rx_watermark_o	Yes	Yes	T131,T333,T132	Yes	T131,T333,T132	OUTPUT
intr_tx_done_o	Yes	Yes	T131,T333,T132	Yes	T131,T333,T132	OUTPUT
intr_rx_overflow_o	Yes	Yes	T131,T333,T132	Yes	T131,T333,T132	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T333,T338,T339	Yes	T333,T338,T339	OUTPUT
intr_rx_break_err_o	Yes	Yes	T333,T338,T339	Yes	T333,T338,T339	OUTPUT
intr_rx_timeout_o	Yes	Yes	T333,T338,T339	Yes	T333,T338,T339	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T333,T338,T339	Yes	T333,T338,T339	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T102,*T103,*T104	Yes	T102,T103,T104	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	INPUT
tl_i.a_valid	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	INPUT
tl_o.a_ready	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	OUTPUT
tl_o.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	OUTPUT
tl_o.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T104,*T162,*T411	Yes	T102,T103,T104	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T104,T105	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T32,*T78,*T79	Yes	T32,T78,T79	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T198,T87,T106	Yes	T198,T87,T106	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T106,T107,T196	Yes	T106,T107,T196	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T106,T107,T196	Yes	T106,T107,T196	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T198,T87,T106	Yes	T198,T87,T106	OUTPUT
cio_rx_i	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	INPUT
cio_tx_o	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	OUTPUT
intr_tx_empty_o	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	OUTPUT
intr_rx_watermark_o	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	OUTPUT
intr_tx_done_o	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	OUTPUT
intr_rx_overflow_o	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T333,T338,T339	Yes	T333,T338,T339	OUTPUT
intr_rx_break_err_o	Yes	Yes	T333,T338,T339	Yes	T333,T338,T339	OUTPUT
intr_rx_timeout_o	Yes	Yes	T333,T338,T339	Yes	T333,T338,T339	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T333,T338,T339	Yes	T333,T338,T339	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T31,T333,T15	Yes	T31,T333,T15	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T31,T333,T15	Yes	T31,T333,T15	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T102,*T103,*T104	Yes	T102,T103,T104	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	INPUT
tl_i.a_valid	Yes	Yes	T31,T198,T87	Yes	T31,T198,T87	INPUT
tl_o.a_ready	Yes	Yes	T31,T198,T87	Yes	T31,T198,T87	OUTPUT
tl_o.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T31,T333,T15	Yes	T31,T333,T15	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T31,T198,T333	Yes	T31,T198,T87	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T31,T198,T333	Yes	T31,T198,T87	OUTPUT
tl_o.d_sink	Yes	Yes	T103,T104,T162	Yes	T102,T103,T104	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T104,*T162,*T411	Yes	T102,T103,T104	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T102,T104,T105	Yes	T102,T103,T104	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T31,*T333,*T15	Yes	T31,T333,T15	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T31,T198,T87	Yes	T31,T198,T87	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T198,T87,T106	Yes	T198,T87,T106	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T106,T107,T196	Yes	T106,T107,T196	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T106,T107,T196	Yes	T106,T107,T196	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T198,T87,T106	Yes	T198,T87,T106	OUTPUT
cio_rx_i	Yes	Yes	T31,T80,T134	Yes	T31,T80,T134	INPUT
cio_tx_o	Yes	Yes	T31,T80,T134	Yes	T31,T80,T134	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T31,T333,T80	Yes	T31,T333,T80	OUTPUT
intr_tx_empty_o	Yes	Yes	T31,T333,T80	Yes	T31,T333,T80	OUTPUT
intr_rx_watermark_o	Yes	Yes	T31,T333,T80	Yes	T31,T333,T80	OUTPUT
intr_tx_done_o	Yes	Yes	T31,T333,T80	Yes	T31,T333,T80	OUTPUT
intr_rx_overflow_o	Yes	Yes	T31,T333,T80	Yes	T31,T333,T80	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T333,T338,T339	Yes	T333,T338,T339	OUTPUT
intr_rx_break_err_o	Yes	Yes	T333,T338,T339	Yes	T333,T338,T339	OUTPUT
intr_rx_timeout_o	Yes	Yes	T333,T338,T339	Yes	T333,T338,T339	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T333,T338,T339	Yes	T333,T338,T339	OUTPUT

*Tests covering at least one bit in the range