Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.82	92.11		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T102,T104,T187	Yes	T102,T103,T104	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T187,T266,T267	Yes	T187,T266,T267	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T219,T94,T57	Yes	T219,T94,T57	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T50,T219,T94	Yes	T50,T219,T94	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T103,T105,T163	Yes	T103,T105,T163	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T48,T49,T50	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T94,T95,T97	Yes	T94,T95,T97	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T48,T49,T50	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T48,T49,T50	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T94,T95,T97	Yes	T94,T95,T97	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T48,T49,T50	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T94,T95,T97	Yes	T94,T95,T97	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T94,T95,T97	Yes	T94,T95,T97	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T95,T97,T41	Yes	T95,T97,T41	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T94,T95,T97	Yes	T94,T95,T97	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T94,*T95,*T97	Yes	T94,T95,T97	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T94,T95,T97	Yes	T94,T95,T97	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T64,T65,T102	Yes	T64,T65,T102	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T64,T65,T102	Yes	T64,T65,T102	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T64,T65,T102	Yes	T64,T65,T102	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T64,T65,T102	Yes	T64,T65,T102	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T64,T65,T102	Yes	T64,T65,T102	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T64,*T65,T102	Yes	T64,T65,T102	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T64,T65,T102	Yes	T64,T65,T102	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T64,T65,T102	Yes	T64,T65,T102	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T102,T104,T105	Yes	T102,T104,T105	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T64,T102,T103	Yes	T64,T102,T103	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T64,T65,T102	Yes	T64,T65,T102	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T64,T65,T102	Yes	T64,T65,T102	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T64,*T65,T104	Yes	T64,T65,T102	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T64,*T65,*T102	Yes	T64,T65,T102	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T64,T65,T102	Yes	T64,T65,T102	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T94,T64,T271	Yes	T94,T64,T271	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T94,T64,T271	Yes	T94,T64,T271	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T94,T64,T271	Yes	T94,T64,T271	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T94,T64,T271	Yes	T94,T64,T271	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T94,T64,T271	Yes	T94,T64,T271	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T94,*T271,*T272	Yes	T94,T271,T272	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T94,T64,T271	Yes	T94,T64,T271	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T48,T49,T50	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T94,T271,T272	Yes	T94,T271,T272	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T94,T64,T271	Yes	T94,T64,T271	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T48,T49,T50	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T94,*T271,*T272	Yes	T94,T271,T272	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T48,T49,T50	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T94,T64,T271	Yes	T94,T64,T271	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T212,T213	Yes	T1,T212,T213	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T212,T304,T41	Yes	T212,T304,T41	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T102,*T103,*T104	Yes	T102,T103,T104	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T87,T64,T88	Yes	T87,T64,T88	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T87,T429,T281	Yes	T87,T429,T281	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T87,T429,T281	Yes	T87,T429,T281	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T87,T64,T88	Yes	T87,T64,T88	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T87,T429,T281	Yes	T87,T429,T281	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T102	Yes	T64,T65,T102	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T87,T429,T281	Yes	T87,T429,T281	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T87,T429,T281	Yes	T87,T429,T281	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T429,T281,T430	Yes	T429,T281,T430	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T64,T65,T103	Yes	T87,T64,T88	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T429,T281,T64	Yes	T87,T429,T281	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T103,T104,T162	Yes	T102,T103,T104	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T64,*T65,T103	Yes	T64,T65,T103	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T281,*T64,*T431	Yes	T429,T281,T64	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T87,T429,T281	Yes	T87,T429,T281	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T49,T660,T661	Yes	T49,T660,T661	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T81,*T102,*T103	Yes	T81,T102,T103	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T13,T239,T240	Yes	T13,T239,T240	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T104,T105,T162	Yes	T104,T105,T162	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T103,T104,T162	Yes	T104,T162,T187	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T81,*T104,*T162	Yes	T81,T102,T103	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T103,T104,T105	Yes	T102,T103,T104	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T12,*T13,*T14	Yes	T12,T13,T14	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T412,T87,T128	Yes	T412,T87,T128	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T412,T87,T128	Yes	T412,T87,T128	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T412,T87,T128	Yes	T412,T87,T128	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T412,T87,T128	Yes	T412,T87,T128	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T412,T87,T128	Yes	T412,T87,T128	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T412,T87,T128	Yes	T412,T87,T128	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T81,*T102,*T103	Yes	T81,T102,T103	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T412,T87,T128	Yes	T412,T87,T128	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T412,T87,T128	Yes	T412,T87,T128	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T412,T128,T15	Yes	T412,T128,T15	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T412,T128,T432	Yes	T412,T87,T128	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T412,T128,T15	Yes	T412,T128,T15	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T81,*T103,*T104	Yes	T81,T102,T103	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T103,T104,T105	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T412,*T128,*T432	Yes	T412,T128,T432	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T412,T87,T128	Yes	T412,T87,T128	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T38,T9,T10	Yes	T38,T9,T10	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T38,T9,T10	Yes	T38,T9,T10	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T38,T9,T10	Yes	T38,T9,T10	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T38,T9,T10	Yes	T38,T9,T10	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T102,*T103,*T104	Yes	T102,T103,T104	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T38,T9,T10	Yes	T38,T9,T10	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T38,T9,T10	Yes	T38,T9,T10	INPUT
tl_usbdev_i.d_error	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T9,T10,T11	Yes	T38,T9,T10	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T38,T9,T10	Yes	T9,T10,T11	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T38,T9,T10	Yes	T9,T10,T11	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T103,*T104,*T162	Yes	T102,T103,T104	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T9,*T10,*T11	Yes	T9,T10,T11	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T38,T9,T10	Yes	T38,T9,T10	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T102,*T103,*T104	Yes	T102,T103,T104	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T8,T27,T48	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T8,T5,T27	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T104,*T162,*T187	Yes	T103,T104,T162	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T102,T104,T105	Yes	T102,T103,T104	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T102,*T103,*T104	Yes	T102,T103,T104	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T4,T38,T9	Yes	T4,T38,T9	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T8,T27,T48	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T102,*T103,*T104	Yes	T102,T103,T104	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_hmac_o.d_ready	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T87,T335,T336	Yes	T87,T335,T336	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T87,T335,T336	Yes	T87,T335,T336	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T87,T335,T336	Yes	T87,T335,T336	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T87,T335,T336	Yes	T87,T335,T336	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T87,T335,T336	Yes	T87,T335,T336	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T102,*T103,*T104	Yes	T102,T103,T104	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T335,T336,T656	Yes	T335,T336,T656	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T87,T335,T336	Yes	T87,T335,T336	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T87,T335,T336	Yes	T87,T335,T336	INPUT
tl_hmac_i.d_error	Yes	Yes	T102,T103,T104	Yes	T104,T105,T162	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T335,T336,T656	Yes	T335,T336,T656	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T335,T336,T656	Yes	T335,T336,T656	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T87,T335,T336	Yes	T335,T336,T656	INPUT
tl_hmac_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T104,T162	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T104,*T162,*T411	Yes	T103,T104,T162	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T87,*T335,*T336	Yes	T335,T336,T656	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T87,T335,T336	Yes	T87,T335,T336	INPUT
tl_kmac_o.d_ready	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T447,T87,T226	Yes	T447,T87,T226	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T447,T42,T206	Yes	T447,T42,T206	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T447,T42,T206	Yes	T447,T42,T206	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T447,T87,T226	Yes	T447,T87,T226	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T447,T42,T206	Yes	T447,T42,T206	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T81,*T102,*T103	Yes	T81,T102,T103	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T447,T448,T449	Yes	T447,T448,T449	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T447,T42,T206	Yes	T447,T42,T206	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T447,T42,T206	Yes	T447,T42,T206	INPUT
tl_kmac_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T447,T42,T206	Yes	T447,T42,T206	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T447,T42,T206	Yes	T447,T42,T206	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T447,T42,T206	Yes	T447,T42,T208	INPUT
tl_kmac_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T81,*T102,*T104	Yes	T81,T102,T103	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T447,*T42,*T206	Yes	T447,T42,T208	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T447,T42,T206	Yes	T447,T42,T206	INPUT
tl_aes_o.d_ready	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T653,T654,T655	Yes	T653,T654,T655	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T653,T654,T655	Yes	T653,T654,T655	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T653,T654,T655	Yes	T653,T654,T655	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T653,T654,T655	Yes	T653,T654,T655	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T653,T654,T655	Yes	T653,T654,T655	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T64,*T102,*T103	Yes	T64,T102,T103	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T653,T654,T655	Yes	T653,T654,T655	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T653,T654,T655	Yes	T653,T654,T655	INPUT
tl_aes_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T653,T654,T655	Yes	T653,T654,T655	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T653,T654,T655	Yes	T653,T654,T655	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T653,T654,T655	Yes	T653,T654,T655	INPUT
tl_aes_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T64,*T104,*T162	Yes	T64,T102,T103	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T102,T104,T105	Yes	T102,T103,T104	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T653,*T654,*T655	Yes	T653,T654,T655	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T653,T654,T655	Yes	T653,T654,T655	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T102,*T103,*T104	Yes	T102,T103,T104	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T102,T104,T105	Yes	T102,T104,T105	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T159,T160,T161	Yes	T159,T160,T161	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T104,*T162,*T411	Yes	T102,T103,T104	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T103,T104,T105	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T159,*T160,*T161	Yes	T159,T160,T161	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T450,T87,T159	Yes	T450,T87,T159	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T64,*T102,*T103	Yes	T64,T102,T103	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T102,T103,T105	Yes	T102,T103,T105	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T450,T159,T160	Yes	T450,T159,T160	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T64,*T103,*T104	Yes	T64,T102,T103	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T450,*T159,*T160	Yes	T450,T159,T160	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T450,T87,T159	Yes	T450,T87,T159	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T450,T87,T159	Yes	T450,T87,T159	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T102,*T103,*T104	Yes	T102,T103,T104	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T450,T159,T160	Yes	T450,T159,T160	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T104,*T162,*T187	Yes	T102,T103,T104	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T104,T105,T162	Yes	T102,T103,T104	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T450,*T159,*T160	Yes	T450,T159,T160	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T87,T159,T160	Yes	T87,T159,T160	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T87,T159,T160	Yes	T87,T159,T160	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T87,T159,T160	Yes	T87,T159,T160	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T87,T159,T160	Yes	T87,T159,T160	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T87,T159,T160	Yes	T87,T159,T160	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T102,*T104,*T162	Yes	T102,T104,T162	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T87,T159,T160	Yes	T87,T159,T160	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T87,T159,T160	Yes	T87,T159,T160	INPUT
tl_edn1_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T159,T160,T161	Yes	T159,T160,T161	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T159,T161,T156	Yes	T87,T159,T160	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T159,T161,T156	Yes	T87,T159,T160	INPUT
tl_edn1_i.d_sink	Yes	Yes	T102,T104,T162	Yes	T104,T162,T187	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T104,*T162,*T187	Yes	T102,T104,T162	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T159,*T160,*T161	Yes	T159,T160,T161	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T87,T159,T160	Yes	T87,T159,T160	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T8,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T81,*T102,*T103	Yes	T81,T102,T103	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T81,*T104,*T162	Yes	T81,T102,T103	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_otbn_o.d_ready	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T223,T87,T159	Yes	T223,T87,T159	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T223,T87,T159	Yes	T223,T87,T159	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T223,T87,T159	Yes	T223,T87,T159	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T223,T87,T159	Yes	T223,T87,T159	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T223,T87,T159	Yes	T223,T87,T159	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T41,*T242,*T243	Yes	T41,T242,T243	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T223,T87,T159	Yes	T223,T87,T159	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T223,T87,T159	Yes	T223,T87,T159	INPUT
tl_otbn_i.d_error	Yes	Yes	T102,T104,T105	Yes	T102,T104,T105	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T223,T159,T156	Yes	T223,T159,T156	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T223,T159,T156	Yes	T223,T159,T156	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T223,T87,T159	Yes	T223,T159,T156	INPUT
tl_otbn_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T41,*T242,*T243	Yes	T41,T242,T243	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T223,*T87,*T159	Yes	T223,T159,T156	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T223,T87,T159	Yes	T223,T87,T159	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T42,T208,T214	Yes	T42,T208,T214	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T42,T206,T208	Yes	T42,T206,T208	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T42,T206,T208	Yes	T42,T206,T208	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T42,T208,T214	Yes	T42,T208,T214	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T42,T206,T208	Yes	T42,T206,T208	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T102,*T103,*T104	Yes	T102,T103,T104	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T42,T206,T208	Yes	T42,T206,T208	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T42,T206,T208	Yes	T42,T206,T208	INPUT
tl_keymgr_i.d_error	Yes	Yes	T104,T105,T162	Yes	T104,T105,T162	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T42,T208,T214	Yes	T42,T208,T214	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T42,T208,T214	Yes	T42,T208,T214	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T42,T208,T214	Yes	T42,T208,T214	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T104,*T162,*T163	Yes	T102,T103,T104	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T102,T103,T105	Yes	T102,T104,T105	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T42,*T208,*T214	Yes	T42,T206,T208	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T42,T206,T208	Yes	T42,T206,T208	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T64,*T273,*T65	Yes	T64,T273,T65	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T64,T65,T102	Yes	T64,T65,T102	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T8,T5,T6	Yes	T8,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T8,T5,T6	Yes	T8,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T64,*T65,*T104	Yes	T64,T273,T65	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T87,T216,T150	Yes	T87,T216,T150	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T87,T216,T150	Yes	T87,T216,T150	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T87,T216,T150	Yes	T87,T216,T150	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T87,T216,T150	Yes	T87,T216,T150	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T87,T216,T150	Yes	T87,T216,T150	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T442,*T443,*T81	Yes	T442,T443,T81	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T87,T216,T150	Yes	T87,T216,T150	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T87,T216,T150	Yes	T87,T216,T150	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T219,T305,T306	Yes	T219,T305,T306	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T216,T150,T219	Yes	T87,T216,T150	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T216,T150,T219	Yes	T87,T216,T150	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T81,*T102,*T104	Yes	T442,T443,T81	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T216,*T150,*T219	Yes	T216,T150,T219	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T87,T216,T150	Yes	T87,T216,T150	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T8,T27,T48	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range