dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[22].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[0].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[1].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[2].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[3].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[4].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[5].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[6].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[7].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[8].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[9].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[10].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[11].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[12].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[13].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[14].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[15].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[16].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[17].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[18].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[19].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[20].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T27 T34 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T27 T34 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T8 T20 T18 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T8 T27 T20 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T27 T20 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T27 T20 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T24 T25 T26 
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T27,T34
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT8,T20,T18
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT27,T29,T30
10CoveredT20,T53,T54
11CoveredT1,T2,T3 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT20,T53,T54
01CoveredT1,T2,T3
10CoveredT20,T53,T54 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T53,T54
11CoveredT20,T53,T54 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT1,T2,T3
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT27,T20,T29
1CoveredT1,T2,T3 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT27,T20,T29
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T27,T20,T29 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T7 T31 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T7 T31 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T7 T33 T45 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T7 T33 T45 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T7 T33 T45 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T7 T33 T45 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T24 T25 T26 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT8,T7,T31
01CoveredT8,T7,T31
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT7,T33,T45
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT7,T33,T45 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT7,T33,T45
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T33,T45 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT7,T33,T45 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T7,T33,T45
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T7 T31 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T7 T31 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T7 T31 T33 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T8 T7 T31 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T7 T31 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T7 T31 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T24 T25 T26 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT8,T7,T31
01CoveredT7,T31,T33
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT7,T31,T33
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T7,T31 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT8,T7,T31
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T7,T31 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T7,T31 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T8,T7,T31
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T7 T12 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T7 T12 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T8 T7 T33 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T8 T7 T33 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T7 T33 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T7 T33 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T12 T51 T52 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT7,T33,T41
01CoveredT8,T7,T12
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT8,T7,T33
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T7,T33 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT8,T7,T33
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T7,T33 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T7,T33 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T51,T52
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T8,T7,T33
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T12,T51,T52
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T27 T7 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T27 T7 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T7 T33 T45 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T7 T33 T45 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T7 T33 T45 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T7 T33 T45 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T24 T25 T26 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT8,T27,T7
01CoveredT8,T7,T33
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT7,T33,T45
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT7,T33,T45 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT7,T33,T45
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T33,T45 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT7,T33,T45 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T7,T33,T45
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T7 T32 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T7 T32 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T8 T7 T33 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T8 T7 T33 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T7 T33 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T7 T33 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T24 T25 T26 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT7,T32,T33
01CoveredT8,T7,T32
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT8,T7,T33
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T7,T33 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT8,T7,T33
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T7,T33 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T7,T33 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T8,T7,T33
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T7 T32 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T7 T32 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T8 T7 T32 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T8 T7 T32 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T7 T32 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T7 T32 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T24 T25 T26 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT7,T32,T33
01CoveredT8,T7,T32
10CoveredT24,T26,T230
11CoveredT24,T26,T230 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT8,T7,T32
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T7,T32 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT8,T7,T32
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T7,T32 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T7,T32 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T8,T7,T32
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T7 T33 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T7 T33 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T7 T33 T45 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T7 T33 T45 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T7 T33 T45 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T7 T33 T45 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T24 T25 T26 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT8,T7,T33
01CoveredT8,T7,T33
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT7,T33,T45
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT7,T33,T45 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT7,T33,T45
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T33,T45 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT7,T33,T45 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T7,T33,T45
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T7 T16 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T7 T16 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T7 T33 T45 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T7 T16 T33 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T7 T16 T33 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T7 T16 T33 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T17 T55 T56 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT8,T7,T16
01CoveredT8,T7,T17
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT7,T33,T45
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT7,T16,T33 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT7,T16,T33
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T16,T33 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT7,T16,T33 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T55,T56
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T7,T16,T33
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T17,T55,T56
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T7 T16 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T7 T16 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T33 T45 T46 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T8 T33 T73 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T33 T73 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T33 T73 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T24 T25 T26 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT8,T7,T16
01CoveredT7,T16,T33
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT33,T45,T46
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T33,T73 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT8,T33,T73
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T33,T73 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T33,T73 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T8,T33,T73
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T12 T41 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T12 T41 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T13 T14 T15 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T8 T13 T14 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T13 T14 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T13 T14 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T12 T51 T52 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT8,T41,T64
01CoveredT12,T15,T51
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT13,T14,T15
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T15,T28 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT8,T15,T28
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T15,T28 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T15,T28 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T51,T52
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T8,T15,T28
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T12,T51,T52
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T12 T13 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T12 T13 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T12 T15 T51 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T12 T15 T28 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T12 T15 T28 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T12 T15 T28 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T12 T13 T14 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT8,T41,T64
01CoveredT8,T12,T13
10CoveredT24,T25,T26
11CoveredT24,T26,T230 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT12,T15,T51
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT15,T28,T85 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT15,T28,T85
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T28,T85 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT15,T28,T85 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T13,T14
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T15,T28,T85
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T12,T13,T14
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T16 T41 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T16 T41 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T15 T85 T130 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T15 T85 T130 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T15 T85 T130 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T15 T85 T130 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T24 T25 T26 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT8,T16,T41
01CoveredT8,T15,T28
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT15,T85,T130
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT15,T85,T130 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT15,T85,T130
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T85,T130 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT15,T85,T130 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T15,T85,T130
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T12 T13 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T12 T13 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T23 T24 T25 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T15 T28 T85 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T15 T28 T85 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T15 T28 T85 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T12 T13 T14 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT8,T34,T18
01CoveredT8,T12,T13
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT23,T24,T25
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT15,T28,T85 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT15,T28,T85
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T28,T85 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT15,T28,T85 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T13,T14
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T15,T28,T85
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T12,T13,T14
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T16 T12 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T16 T12 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T8 T15 T28 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T8 T15 T28 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T15 T28 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T15 T28 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T12 T15 T51 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT16,T131,T41
01CoveredT8,T12,T131
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT8,T15,T28
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T15,T28 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT8,T15,T28
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T15,T28 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T15,T28 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T15,T51
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T8,T15,T28
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T12,T15,T51
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T1 T2 T3 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T1 T2 T3 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T1 T2 T3 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T1 T2 T3 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T1 T2 T3 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T1 T2 T3 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T12 T15 T51 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT8,T131,T41
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT1,T2,T3
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT1,T2,T3
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T15,T51
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T12,T15,T51
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T12 T33 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T12 T33 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T8 T33 T15 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T8 T33 T15 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T33 T15 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T33 T15 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T12 T15 T51 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT33,T34,T18
01CoveredT8,T12,T33
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT8,T33,T15
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T33,T15 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT8,T33,T15
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T33,T15 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T33,T15 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T15,T51
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T8,T33,T15
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T12,T15,T51
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T33 T20 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T33 T20 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T33 T20 T18 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T8 T33 T20 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T33 T20 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T33 T20 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T24 T25 T26 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT8,T33,T20
01CoveredT33,T20,T18
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT33,T20,T18
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T33,T20 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT8,T33,T20
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T33,T20 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T33,T20 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T8,T33,T20
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T33 T34 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T33 T34 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T8 T33 T15 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T8 T33 T15 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T33 T15 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T33 T15 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T24 T25 T26 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT33,T34,T18
01CoveredT8,T33,T34
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT8,T33,T15
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T33,T15 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT8,T33,T15
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T33,T15 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T33,T15 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T8,T33,T15
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T6 T35 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T6 T35 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T6 T33 T18 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T6 T33 T75 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T6 T33 T75 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T6 T33 T75 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T24 T25 T26 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT8,T6,T35
01CoveredT8,T6,T35
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT6,T33,T18
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT6,T33,T75 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT6,T33,T75
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T33,T75 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT6,T33,T75 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T6,T33,T75
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T6 T35 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T6 T35 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T6 T33 T39 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T8 T6 T35 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T6 T35 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T6 T35 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T24 T25 T26 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT8,T6,T35
01CoveredT6,T35,T33
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT6,T33,T39
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T6,T35 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT8,T6,T35
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T6,T35 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T6,T35 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T8,T6,T35
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00


38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T24 T25 T26 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T8 T6 T33 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T8 T6 T33 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T8 T33 T39 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T8 T6 T33 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T6 T33 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T8 T6 T33 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T24 T25 T26 
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT24,T25,T26
11CoveredT1,T2,T3 

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT1,T2,T3 

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT6,T33,T76
01CoveredT8,T33,T76
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT8,T33,T39
11CoveredT24,T25,T26 

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T6,T33 

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT1,T2,T3
10CoveredT24,T25,T26 

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT24,T25,T26 

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26 

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT8,T6,T33
11CoveredT24,T25,T26 

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T6,T33 

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT8,T6,T33 

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T26
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00 



78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T24,T25,T26 



92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3 



93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>

Branches:
-1-StatusTests
1 Covered T8,T6,T33
0 Covered T1,T2,T3 



95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1030 1030 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%