Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.82	92.11		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T49,T660,T661	Yes	T49,T660,T661	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T126,T36,T262	Yes	T126,T36,T262	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T126,T36,T262	Yes	T126,T36,T262	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T126,T36,T198	Yes	T126,T36,T198	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T126,T36,T198	Yes	T126,T36,T198	INPUT
tl_uart0_i.d_error	Yes	Yes	T104,T105,T162	Yes	T103,T104,T105	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T126,T36,T333	Yes	T126,T36,T333	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T126,T36,T198	Yes	T126,T36,T198	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T126,T36,T198	Yes	T126,T36,T198	INPUT
tl_uart0_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T271,*T273,*T104	Yes	T271,T273,T102	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T126,*T36,*T333	Yes	T126,T36,T333	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T126,T36,T198	Yes	T126,T36,T198	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T131,T333,T15	Yes	T131,T333,T15	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T131,T333,T15	Yes	T131,T333,T15	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T131,T198,T87	Yes	T131,T198,T87	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T131,T198,T87	Yes	T131,T198,T87	INPUT
tl_uart1_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T131,T333,T15	Yes	T131,T333,T15	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T131,T198,T333	Yes	T131,T198,T87	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T131,T198,T333	Yes	T131,T198,T87	INPUT
tl_uart1_i.d_sink	Yes	Yes	T102,T104,T162	Yes	T102,T104,T162	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T104,*T162,*T163	Yes	T102,T104,T162	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T104,T105	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T131,*T333,*T15	Yes	T131,T333,T15	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T131,T198,T87	Yes	T131,T198,T87	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	INPUT
tl_uart2_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	INPUT
tl_uart2_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T104,*T162,*T411	Yes	T102,T103,T104	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T104,T105	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T32,*T78,*T79	Yes	T32,T78,T79	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T32,T78,T79	Yes	T32,T78,T79	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T31,T333,T15	Yes	T31,T333,T15	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T31,T333,T15	Yes	T31,T333,T15	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T31,T198,T87	Yes	T31,T198,T87	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T31,T198,T87	Yes	T31,T198,T87	INPUT
tl_uart3_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T31,T333,T15	Yes	T31,T333,T15	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T198,T333	Yes	T31,T198,T87	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T31,T198,T333	Yes	T31,T198,T87	INPUT
tl_uart3_i.d_sink	Yes	Yes	T103,T104,T162	Yes	T102,T103,T104	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T104,*T162,*T411	Yes	T102,T103,T104	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T102,T104,T105	Yes	T102,T103,T104	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T31,*T333,*T15	Yes	T31,T333,T15	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T31,T198,T87	Yes	T31,T198,T87	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T73,T412,T340	Yes	T73,T412,T340	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T73,T412,T340	Yes	T73,T412,T340	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T73,T412,T198	Yes	T73,T412,T198	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T73,T412,T198	Yes	T73,T412,T198	INPUT
tl_i2c0_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T73,T340,T15	Yes	T73,T340,T15	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T73,T412,T198	Yes	T73,T412,T198	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T73,T412,T198	Yes	T73,T412,T198	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T104,*T162,*T411	Yes	T102,T103,T104	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T102,T104,T105	Yes	T102,T103,T104	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T73,*T412,*T340	Yes	T73,T412,T340	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T73,T412,T198	Yes	T73,T412,T198	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T35,T75,T412	Yes	T35,T75,T412	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T35,T75,T412	Yes	T35,T75,T412	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T35,T75,T412	Yes	T35,T75,T412	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T35,T75,T412	Yes	T35,T75,T412	INPUT
tl_i2c1_i.d_error	Yes	Yes	T102,T104,T105	Yes	T102,T103,T104	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T35,T75,T340	Yes	T35,T75,T340	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T35,T75,T412	Yes	T35,T75,T412	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T35,T75,T412	Yes	T35,T75,T412	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T102,T104,T162	Yes	T102,T103,T104	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T104,*T162,*T411	Yes	T102,T103,T104	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T102,T104,T105	Yes	T102,T104,T105	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T35,*T75,*T412	Yes	T35,T75,T412	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T35,T75,T412	Yes	T35,T75,T412	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T76,T412,T340	Yes	T76,T412,T340	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T76,T412,T340	Yes	T76,T412,T340	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T76,T412,T198	Yes	T76,T412,T198	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T76,T412,T198	Yes	T76,T412,T198	INPUT
tl_i2c2_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T76,T340,T15	Yes	T76,T340,T15	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T76,T412,T198	Yes	T76,T412,T198	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T76,T412,T198	Yes	T76,T412,T198	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T104,*T162,*T411	Yes	T102,T103,T104	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T76,*T412,*T340	Yes	T76,T412,T340	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T76,T412,T198	Yes	T76,T412,T198	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T6,T128,T15	Yes	T6,T128,T15	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T6,T128,T15	Yes	T6,T128,T15	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T6,T87,T128	Yes	T6,T87,T128	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T6,T87,T128	Yes	T6,T87,T128	INPUT
tl_pattgen_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T6,T128,T15	Yes	T6,T128,T15	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T128,T15	Yes	T6,T87,T128	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T6,T128,T15	Yes	T6,T87,T128	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T102,T104,T162	Yes	T102,T103,T104	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T81,*T104,*T162	Yes	T81,T103,T104	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T6,*T128,*T15	Yes	T6,T128,T15	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T6,T87,T128	Yes	T6,T87,T128	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T39,T86,T136	Yes	T39,T86,T136	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T39,T86,T136	Yes	T39,T86,T136	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T39,T87,T86	Yes	T39,T87,T86	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T39,T87,T86	Yes	T39,T87,T86	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T102,T105,T162	Yes	T102,T105,T162	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T39,T86,T136	Yes	T39,T86,T136	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T39,T86,T136	Yes	T39,T87,T86	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T39,T86,T136	Yes	T39,T87,T86	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T64,*T65,*T104	Yes	T64,T65,T102	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T103,T104,T105	Yes	T102,T103,T104	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T39,*T86,*T136	Yes	T39,T86,T136	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T39,T87,T86	Yes	T39,T87,T86	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_gpio_i.d_error	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T16,T33,T340	Yes	T16,T33,T340	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T33,T340	Yes	T7,T16,T33	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T16,T33,T340	Yes	T7,T16,T33	INPUT
tl_gpio_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T103,T104,T162	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T104,*T162,*T187	Yes	T102,T103,T104	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T8,*T27,*T7	Yes	T2,T3,T4	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T16,T17,T13	Yes	T16,T17,T13	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T16,T17,T13	Yes	T16,T17,T13	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T16,T17,T13	Yes	T16,T17,T13	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T16,T17,T13	Yes	T16,T17,T13	INPUT
tl_spi_device_i.d_error	Yes	Yes	T103,T104,T105	Yes	T102,T103,T104	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T17,T13,T14	Yes	T17,T13,T14	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T17,T13	Yes	T16,T17,T13	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T16,T17,T13	Yes	T17,T13,T14	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T103,T104,T162	Yes	T102,T103,T104	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T81,*T103,*T104	Yes	T81,T102,T103	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T16,*T17,*T13	Yes	T16,T17,T13	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T16,T17,T13	Yes	T16,T17,T13	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T127,T252,T645	Yes	T127,T252,T645	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T127,T252,T645	Yes	T127,T252,T645	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T127,T252,T87	Yes	T127,T252,T87	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T127,T252,T87	Yes	T127,T252,T87	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T127,T252,T645	Yes	T127,T252,T645	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T127,T252,T645	Yes	T127,T252,T87	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T127,T252,T645	Yes	T127,T252,T87	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T81,*T103,*T104	Yes	T81,T102,T103	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T127,*T252,*T645	Yes	T127,T252,T645	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T127,T252,T87	Yes	T127,T252,T87	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T8,T27,T7	Yes	T8,T27,T7	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T8,T27,T7	Yes	T8,T27,T7	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T8,T27,T7	Yes	T8,T27,T7	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T8,T27,T7	Yes	T8,T27,T7	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T102,T103,T105	Yes	T102,T103,T105	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T8,T27,T7	Yes	T8,T27,T7	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T27,T7	Yes	T8,T27,T7	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T8,T27,T7	Yes	T8,T27,T7	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T64,*T65,*T103	Yes	T64,T65,T102	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T8,*T27,*T7	Yes	T8,T27,T7	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T8,T27,T7	Yes	T8,T27,T7	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T103,T104,T105	Yes	T102,T103,T104	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T27,T48,T49	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T27,T48,T49	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T64,*T65,*T104	Yes	T64,T65,T102	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T103,T104,T105	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T31,T32,T126	Yes	T31,T32,T126	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T31,T32,T126	Yes	T31,T32,T126	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T31,T32,T126	Yes	T31,T32,T126	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T48,T49,T31	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T48,T49,T31	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T64,*T102,*T104	Yes	T64,T189,T190	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T104,T105	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T31,*T32,*T126	Yes	T31,T32,T126	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T64,*T65,*T81	Yes	T64,T65,T81	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T102,T104,T105	Yes	T102,T104,T105	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T104,T162,T187	Yes	T104,T162,T187	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T188,*T189,*T190	Yes	T188,T189,T190	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T103,T104,T105	Yes	T104,T105,T162	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T191,*T40,*T42	Yes	T191,T42,T192	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T81,T102,T103	Yes	T81,T102,T103	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T81,T103,T104	Yes	T81,T103,T104	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T81,T102,T103	Yes	T81,T102,T103	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T2,T3	Yes	T48,T49,T50	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T81,T102,T103	Yes	T81,T102,T103	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T81,T103,T104	Yes	T81,T102,T103	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T48,T49,T50	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T81,*T102,T103	Yes	T81,T102,T103	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T48,T49,T50	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T81,T102,T103	Yes	T81,T102,T103	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T5,T36,T191	Yes	T5,T36,T191	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T5,T36,T191	Yes	T5,T36,T191	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T5,T36,T191	Yes	T5,T36,T191	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T5,T36,T191	Yes	T5,T36,T191	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T191,T42,T62	Yes	T5,T191,T42	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T62,T205,T228	Yes	T62,T205,T228	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T191,T42,T62	Yes	T5,T36,T191	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T94,*T360,*T361	Yes	T94,T360,T361	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T42,*T62,*T208	Yes	T5,T36,T191	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T5,T36,T191	Yes	T5,T36,T191	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T181,T165,T167	Yes	T181,T165,T167	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T181,T165,T167	Yes	T87,T181,T165	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T48,T49,T50	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T103,T104,T162	Yes	T103,T104,T162	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T81,*T103,*T104	Yes	T81,T102,T103	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T48,*T49,*T50	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T64,*T102,*T104	Yes	T64,T102,T103	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T48,*T49,*T50	Yes	T48,T49,T50	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T216,T150,T218	Yes	T216,T150,T218	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T216,T150,T218	Yes	T216,T150,T218	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T87,T216,T150	Yes	T87,T216,T150	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T87,T216,T150	Yes	T87,T216,T150	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T216,T150,T218	Yes	T216,T150,T218	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T216,T150,T218	Yes	T87,T216,T150	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T216,T150,T218	Yes	T87,T216,T150	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T81,*T102,*T103	Yes	T81,T102,T103	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T216,*T150,*T218	Yes	T216,T150,T218	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T87,T216,T150	Yes	T87,T216,T150	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T27,T48,T49	Yes	T27,T48,T49	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T48,T49,T50	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T48,T49,T50	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T41,*T271,*T242	Yes	T41,T271,T242	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T103,T104,T162	Yes	T103,T104,T162	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T64,*T103,*T104	Yes	T64,T271,T659	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T48,*T49,*T50	Yes	T48,T49,T50	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T34,T83,T84	Yes	T34,T83,T84	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T34,T83,T84	Yes	T34,T83,T84	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T34,T83,T84	Yes	T34,T83,T84	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T34,T83,T84	Yes	T34,T83,T84	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T34,T83,T84	Yes	T34,T83,T84	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T83,T84,T137	Yes	T83,T84,T137	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T34,T83,T84	Yes	T34,T83,T84	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T81,*T103,*T104	Yes	T81,T102,T103	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T83,*T84,*T137	Yes	T34,T83,T84	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T34,T83,T84	Yes	T34,T83,T84	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T140,T340,T63	Yes	T140,T340,T63	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T140,T340,T63	Yes	T140,T340,T63	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T140,T87,T340	Yes	T140,T87,T340	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T140,T87,T340	Yes	T140,T87,T340	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T140,T340,T68	Yes	T140,T340,T63	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T140,T340,T63	Yes	T140,T87,T340	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T140,T63,T68	Yes	T140,T87,T340	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T64,*T104,*T162	Yes	T64,T102,T103	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T103,T104,T105	Yes	T102,T103,T104	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T140,*T340,*T68	Yes	T140,T340,T63	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T140,T87,T340	Yes	T140,T87,T340	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T94,*T41,*T64	Yes	T94,T41,T64	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T102,T103,T104	Yes	T103,T104,T162	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T8,T27,T48	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T104,*T162,*T163	Yes	T102,T103,T104	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T103,*T104,*T162	Yes	T103,T104,T162	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range