Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.pinmux_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	138630	1			T94	6		T95	2		T96	8
values[2]	9601	1			T554	1		T562	1		T427	88
values[3]	3510	1			T427	59		T570	4		T434	70
values[4]	2275	1			T427	35		T570	1		T434	58
values[5]	1606	1			T427	46		T570	1		T434	59
values[6]	1118	1			T427	54		T570	5		T434	55
values[7]	994	1			T427	35		T570	1		T434	61
values[8]	743	1			T427	34		T570	1		T434	32
values[9]	594	1			T427	28		T570	3		T434	21
values[10]	486	1			T427	12		T570	5		T434	16
values[11]	453	1			T427	17		T570	7		T434	7
values[12]	367	1			T427	13		T570	6		T434	1
values[13]	374	1			T427	1		T570	4		T522	1
values[14]	319	1			T570	3		T522	1		T472	3
values[15]	322	1			T570	1		T522	1		T472	4
values[16]	354	1			T570	2		T522	1		T472	1
values[17]	348	1			T570	2		T522	1		T472	3
values[18]	295	1			T570	6		T522	1		T472	2
values[19]	291	1			T570	5		T522	1		T472	3
values[20]	302	1			T570	4		T522	1		T472	7
values[21]	275	1			T570	3		T522	1		T472	1
values[22]	287	1			T570	1		T522	1		T472	3
values[23]	292	1			T570	3		T522	1		T472	8
values[24]	277	1			T570	2		T522	1		T472	4
values[25]	307	1			T570	1		T522	1		T472	14
values[26]	298	1			T570	1		T522	1		T472	4
values[27]	290	1			T570	2		T522	1		T472	2
values[28]	282	1			T570	3		T522	1		T472	1
values[29]	266	1			T570	10		T522	1		T472	2
values[30]	282	1			T570	3		T522	1		T472	2
values[31]	301	1			T570	4		T522	1		T472	2
values[32]	307	1			T570	4		T522	1		T472	3
values[33]	274	1			T570	3		T522	1		T472	5
values[34]	276	1			T570	4		T522	1		T472	11
values[35]	335	1			T570	9		T522	1		T472	6
values[36]	274	1			T570	4		T522	1		T472	1
values[37]	254	1			T570	5		T522	1		T472	2
values[38]	271	1			T570	4		T522	1		T472	3
values[39]	275	1			T570	2		T522	1		T472	1
values[40]	241	1			T570	1		T522	1		T472	2
values[41]	263	1			T570	3		T522	1		T472	1
values[42]	280	1			T570	2		T522	1		T472	1
values[43]	268	1			T570	2		T522	1		T472	3
values[44]	280	1			T570	3		T522	1		T472	7
values[45]	279	1			T570	4		T522	1		T472	3
values[46]	243	1			T570	3		T522	1		T472	3
values[47]	227	1			T570	3		T522	1		T472	1
values[48]	235	1			T570	1		T522	1		T472	1
values[49]	247	1			T570	2		T522	1		T472	2
values[50]	226	1			T570	2		T522	1		T472	2
values[51]	264	1			T570	2		T522	1		T472	2
values[52]	273	1			T570	1		T522	1		T472	1
values[53]	214	1			T570	2		T522	1		T472	3
values[54]	198	1			T570	2		T522	1		T472	1
values[55]	239	1			T570	2		T522	2		T472	4
values[56]	224	1			T570	1		T522	1		T472	6
values[57]	253	1			T570	2		T522	1		T472	2
values[58]	213	1			T570	3		T522	1		T472	2
values[59]	230	1			T570	2		T522	1		T472	1
values[60]	208	1			T570	2		T522	1		T472	4
values[61]	192	1			T570	1		T522	1		T472	2
values[62]	209	1			T570	2		T522	1		T472	1
values[63]	166	1			T570	2		T522	1		T472	1
values[64]	162	1			T570	4		T522	1		T472	1
values[65]	156	1			T570	1		T522	1		T472	2
values[66]	162	1			T570	4		T522	1		T472	2
values[67]	143	1			T570	2		T522	1		T472	10
values[68]	151	1			T570	2		T522	1		T472	8
values[69]	143	1			T570	2		T522	1		T472	9
values[70]	125	1			T570	1		T522	1		T472	10
values[71]	158	1			T570	2		T522	1		T472	10
values[72]	172	1			T570	2		T522	2		T472	10
values[73]	152	1			T570	1		T522	1		T472	7
values[74]	135	1			T570	1		T522	1		T472	7
values[75]	119	1			T570	2		T522	1		T472	3
values[76]	115	1			T570	4		T522	1		T472	4
values[77]	119	1			T570	3		T522	1		T472	16
values[78]	108	1			T570	3		T522	1		T472	15
values[79]	96	1			T570	2		T522	1		T472	10
values[80]	114	1			T570	5		T522	1		T472	7
values[81]	99	1			T570	1		T522	1		T472	8
values[82]	108	1			T570	3		T522	1		T472	11
values[83]	92	1			T570	2		T522	1		T472	10
values[84]	120	1			T570	1		T522	1		T472	14
values[85]	84	1			T570	1		T522	1		T472	3
values[86]	107	1			T570	2		T522	1		T472	2
values[87]	135	1			T570	1		T522	2		T472	2
values[88]	108	1			T570	3		T522	2		T472	2
values[89]	123	1			T570	3		T522	2		T472	5
values[90]	94	1			T570	5		T522	2		T472	2
values[91]	111	1			T522	2		T472	6		T541	8
values[92]	111	1			T522	4		T472	4		T541	4
values[93]	110	1			T522	4		T472	6		T541	2
values[94]	92	1			T522	1		T472	2		T541	5
values[95]	96	1			T522	5		T472	7		T541	3
values[96]	121	1			T522	3		T472	7		T541	2
values[97]	108	1			T522	6		T472	11		T541	7
values[98]	80	1			T522	4		T472	6		T541	1
values[99]	104	1			T522	1		T472	4		T541	6
values[100]	113	1			T522	1		T472	7		T541	2
values[101]	102	1			T522	2		T472	11		T541	3
values[102]	96	1			T522	1		T472	2		T541	1
values[103]	95	1			T522	2		T472	5		T541	1
values[104]	91	1			T522	1		T472	2		T541	3
values[105]	80	1			T522	1		T472	2		T541	1
values[106]	106	1			T522	1		T472	2		T541	1
values[107]	96	1			T522	2		T472	2		T541	3
values[108]	98	1			T522	3		T472	1		T541	2
values[109]	85	1			T522	2		T472	1		T541	1
values[110]	94	1			T522	1		T472	7		T541	1
values[111]	89	1			T522	1		T472	7		T541	2
values[112]	90	1			T522	1		T472	6		T541	2
values[113]	85	1			T522	6		T541	3		T490	1
values[114]	90	1			T522	4		T541	4		T490	1
values[115]	81	1			T522	2		T541	4		T490	1
values[116]	81	1			T522	2		T541	4		T490	1
values[117]	71	1			T522	1		T541	1		T490	1
values[118]	64	1			T522	3		T541	1		T490	4
values[119]	58	1			T522	1		T541	1		T490	1
values[120]	76	1			T522	1		T541	2		T490	3
values[121]	59	1			T522	2		T541	1		T490	1
values[122]	45	1			T522	2		T541	1		T490	1
values[123]	64	1			T522	1		T541	4		T490	3
values[124]	65	1			T522	1		T541	3		T490	1
values[125]	72	1			T522	1		T541	1		T490	1
values[126]	136	1			T522	1		T541	3		T490	2
values[127]	1054	1			T522	28		T541	28		T490	39
values[128]	8833	1			T522	303		T541	288		T490	395