Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.20 95.56 94.20 95.32 95.08 97.53 99.53


Total tests in report: 2918
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
39.91 39.91 45.06 45.06 46.66 46.66 26.95 26.95 63.16 63.16 57.52 57.52 0.14 0.14 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1047033246
47.10 7.19 49.17 4.11 55.53 8.87 27.17 0.22 69.14 5.98 80.59 23.08 1.03 0.89 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.646438572
52.40 5.29 60.40 11.23 63.06 7.53 30.17 3.01 79.12 9.98 80.59 0.00 1.03 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.1481183284
56.19 3.80 67.94 7.54 64.33 1.27 36.57 6.39 79.36 0.24 80.59 0.00 8.37 7.33 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.1564910649
59.65 3.46 74.57 6.63 68.47 4.14 41.11 4.54 81.66 2.30 83.74 3.15 8.37 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.1115754360
62.70 3.05 79.41 4.84 72.27 3.80 44.53 3.42 83.34 1.69 88.29 4.55 8.37 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1487741290
65.68 2.98 79.41 0.00 72.45 0.18 44.53 0.00 83.36 0.02 88.29 0.00 26.05 17.68 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3723572005
68.18 2.50 80.89 1.48 74.99 2.54 50.88 6.35 85.02 1.66 88.64 0.35 28.68 2.63 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.626216310
70.59 2.41 80.89 0.00 74.99 0.00 65.32 14.45 85.02 0.00 88.64 0.00 28.68 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.3551188486
72.83 2.24 80.89 0.00 75.17 0.18 65.32 0.00 85.04 0.02 88.64 0.00 41.91 13.23 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.1413986101
74.62 1.80 80.89 0.00 75.26 0.09 65.32 0.00 85.04 0.00 88.64 0.00 52.59 10.68 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.1618623355
76.19 1.56 81.00 0.11 75.35 0.09 74.16 8.83 85.21 0.17 88.81 0.17 52.59 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.3952770775
77.65 1.46 81.00 0.00 75.35 0.00 74.16 0.00 85.21 0.00 88.81 0.00 61.37 8.78 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.18882069
78.99 1.34 83.33 2.33 77.27 1.92 75.26 1.10 87.90 2.69 88.81 0.00 61.37 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.1926953070
80.30 1.31 83.33 0.00 77.39 0.11 75.26 0.00 87.92 0.02 88.81 0.00 69.12 7.75 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.263973351
81.59 1.28 84.58 1.26 79.25 1.86 76.22 0.97 89.33 1.41 90.91 2.10 69.23 0.11 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.1540489207
82.81 1.22 86.84 2.26 80.27 1.02 78.44 2.22 90.09 0.76 91.96 1.05 69.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.3157979734
83.85 1.04 86.84 0.01 80.54 0.27 78.44 0.00 90.14 0.05 91.96 0.00 75.16 5.93 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.3338855245
84.77 0.92 87.95 1.11 81.24 0.70 80.78 2.34 91.17 1.03 92.31 0.35 75.16 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.912982563
85.63 0.86 88.25 0.30 85.75 4.52 80.78 0.00 91.25 0.07 92.31 0.00 75.43 0.27 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.1848309081
86.41 0.78 89.08 0.83 86.42 0.67 83.14 2.35 92.10 0.85 92.31 0.00 75.43 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.2926895692
87.16 0.74 89.42 0.34 86.56 0.13 83.15 0.01 92.23 0.13 96.15 3.85 75.43 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2090346415
87.82 0.66 89.42 0.00 86.56 0.00 83.15 0.00 92.23 0.00 96.15 0.00 79.40 3.97 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.2136761186
88.41 0.59 90.53 1.11 87.15 0.59 84.51 1.36 92.70 0.47 96.15 0.00 79.40 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.2707117764
88.96 0.55 90.53 0.00 87.19 0.04 84.51 0.00 92.70 0.00 96.15 0.00 82.65 3.24 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2733740810
89.47 0.52 91.33 0.79 87.23 0.04 84.63 0.12 92.70 0.00 96.15 0.00 84.80 2.15 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.605915202
89.95 0.47 91.33 0.00 87.23 0.00 84.63 0.00 92.70 0.00 96.15 0.00 87.64 2.84 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.475991545
90.37 0.42 91.33 0.00 87.23 0.00 84.63 0.00 92.70 0.00 96.15 0.00 90.17 2.53 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.696709615
90.76 0.39 91.34 0.01 87.24 0.01 86.78 2.15 92.70 0.00 96.33 0.17 90.17 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.2533316707
91.09 0.33 92.11 0.77 87.56 0.32 87.48 0.69 92.88 0.19 96.33 0.00 90.17 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3544429193
91.42 0.33 92.11 0.00 87.57 0.01 87.48 0.00 92.88 0.00 96.33 0.00 92.14 1.97 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.512539478
91.71 0.29 92.62 0.51 88.06 0.50 87.75 0.27 93.37 0.49 96.33 0.00 92.14 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.2600304510
91.99 0.28 92.62 0.00 88.06 0.00 89.43 1.68 93.37 0.00 96.33 0.00 92.14 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2855313339
92.27 0.28 92.62 0.00 88.06 0.00 89.43 0.00 93.37 0.00 96.33 0.00 93.80 1.66 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.4157146945
92.54 0.28 93.08 0.46 88.60 0.53 89.82 0.39 93.64 0.27 96.33 0.00 93.80 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1999909466
92.80 0.25 93.08 0.00 88.60 0.00 89.82 0.00 93.64 0.00 96.33 0.00 95.31 1.52 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.2396972586
93.05 0.25 93.39 0.31 89.74 1.15 89.83 0.01 93.67 0.03 96.33 0.00 95.31 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.1395212051
93.28 0.23 93.39 0.00 89.78 0.04 89.83 0.00 93.67 0.00 96.33 0.00 96.66 1.35 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.1631955103
93.47 0.20 93.39 0.00 89.78 0.00 91.01 1.18 93.67 0.00 96.33 0.00 96.66 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3731629409
93.64 0.17 93.39 0.00 89.78 0.00 92.04 1.03 93.67 0.00 96.33 0.00 96.66 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.3076191782
93.79 0.14 93.89 0.51 89.98 0.20 92.11 0.07 93.76 0.09 96.33 0.00 96.66 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2385962421
93.93 0.14 93.89 0.00 90.80 0.82 92.11 0.00 93.76 0.00 96.33 0.00 96.67 0.01 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.2792250702
94.07 0.14 93.93 0.04 91.16 0.36 92.14 0.03 94.17 0.41 96.33 0.00 96.67 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3795063358
94.20 0.13 93.93 0.00 91.30 0.14 92.14 0.00 94.17 0.00 96.33 0.00 97.31 0.63 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.2090927968
94.31 0.11 94.11 0.18 91.43 0.13 92.36 0.22 94.31 0.15 96.33 0.00 97.31 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1222006416
94.39 0.09 94.19 0.08 91.69 0.25 92.49 0.13 94.36 0.05 96.33 0.00 97.31 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.3432653047
94.47 0.08 94.28 0.09 91.76 0.08 92.68 0.19 94.47 0.11 96.33 0.00 97.31 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.3496094574
94.55 0.07 94.30 0.02 91.80 0.04 92.86 0.18 94.50 0.02 96.50 0.17 97.31 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.3348089086
94.61 0.06 94.30 0.00 91.80 0.00 93.25 0.39 94.50 0.00 96.50 0.00 97.31 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.4171198919
94.67 0.06 94.40 0.11 91.82 0.02 93.35 0.10 94.50 0.00 96.50 0.00 97.44 0.13 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1238900167
94.73 0.06 94.40 0.00 92.18 0.36 93.35 0.00 94.50 0.00 96.50 0.00 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.3172786653
94.79 0.06 94.40 0.00 92.34 0.16 93.35 0.00 94.68 0.18 96.50 0.00 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3606189542
94.84 0.05 94.43 0.03 92.36 0.02 93.42 0.07 94.70 0.02 96.68 0.17 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.1245080129
94.89 0.05 94.43 0.00 92.38 0.01 93.42 0.00 94.70 0.00 96.68 0.00 97.74 0.31 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.828123840
94.94 0.05 94.43 0.00 92.45 0.08 93.42 0.00 94.75 0.05 96.68 0.00 97.90 0.15 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1199681382
94.99 0.05 94.49 0.06 92.53 0.08 93.55 0.12 94.77 0.02 96.68 0.00 97.90 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1171204399
95.03 0.04 94.49 0.00 92.53 0.00 93.81 0.26 94.77 0.00 96.68 0.00 97.90 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2435382005
95.07 0.04 94.53 0.04 92.58 0.05 93.95 0.14 94.78 0.02 96.68 0.00 97.90 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.3330976304
95.11 0.04 94.54 0.01 92.60 0.02 93.95 0.00 94.81 0.02 96.85 0.17 97.91 0.01 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.2699077974
95.15 0.04 94.54 0.00 92.60 0.01 93.95 0.00 94.81 0.00 96.85 0.00 98.14 0.23 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1094500318
95.19 0.04 94.55 0.01 92.62 0.01 93.96 0.01 94.82 0.01 97.03 0.17 98.16 0.01 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.1206888744
95.22 0.04 94.55 0.01 92.63 0.01 93.97 0.01 94.82 0.01 97.20 0.17 98.17 0.01 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.143138925
95.26 0.04 94.56 0.01 92.64 0.01 93.97 0.00 94.83 0.01 97.38 0.17 98.18 0.01 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3300248947
95.29 0.04 94.63 0.07 92.64 0.00 94.10 0.13 94.84 0.01 97.38 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.1543696219
95.33 0.03 94.63 0.01 92.70 0.05 94.17 0.08 94.89 0.05 97.38 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3569144928
95.35 0.03 94.63 0.00 92.70 0.01 94.17 0.00 94.89 0.00 97.55 0.17 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.1586730273
95.38 0.03 94.70 0.06 92.75 0.05 94.21 0.04 94.91 0.02 97.55 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.872879750
95.41 0.03 94.77 0.07 92.79 0.04 94.23 0.02 94.94 0.02 97.55 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.2673006693
95.43 0.03 94.77 0.00 92.83 0.04 94.23 0.00 94.94 0.00 97.55 0.00 98.30 0.12 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.3980236403
95.46 0.03 94.83 0.07 92.86 0.03 94.24 0.01 94.99 0.05 97.55 0.00 98.30 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.3062815019
95.48 0.02 94.83 0.00 93.00 0.14 94.24 0.00 94.99 0.00 97.55 0.00 98.30 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.634456335
95.51 0.02 94.83 0.00 93.00 0.01 94.36 0.12 94.99 0.00 97.55 0.00 98.31 0.01 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3125434604
95.53 0.02 94.83 0.00 93.06 0.05 94.36 0.00 94.99 0.00 97.55 0.00 98.39 0.08 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.3114878643
95.55 0.02 94.89 0.06 93.10 0.05 94.36 0.00 95.00 0.02 97.55 0.00 98.39 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.2238032894
95.57 0.02 94.91 0.02 93.16 0.06 94.40 0.04 95.00 0.00 97.55 0.00 98.39 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.1526176869
95.59 0.02 94.91 0.00 93.27 0.11 94.40 0.00 95.00 0.00 97.55 0.00 98.39 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.1495571799
95.61 0.02 94.91 0.01 93.31 0.04 94.47 0.07 95.00 0.00 97.55 0.00 98.39 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.1365317217
95.62 0.02 94.91 0.00 93.37 0.06 94.47 0.00 95.02 0.02 97.55 0.00 98.43 0.04 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.2303475371
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96.11 0.01 94.98 0.00 94.20 0.00 95.32 0.01 95.08 0.00 97.55 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.2334382166
96.11 0.01 94.98 0.00 94.20 0.00 95.32 0.01 95.08 0.00 97.55 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3377310767
96.11 0.01 94.98 0.00 94.20 0.00 95.32 0.01 95.08 0.00 97.55 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2478684558

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.2516279919
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.635083521
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.2090008555
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.1519311161
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.656242506
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1763178832
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1999541375
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.1624014052
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.3006557153
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.4292867460
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.3209580632
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.824026249
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2464264374
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.1871825366
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.3563813224
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.2838636221
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.1460275147
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.243201755
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3067282904
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.2474446063
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2863525062
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.1843231770
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.3542201430
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2326110618
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.2389129571
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.1665143817
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.823957212
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.311692545
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.3840993895
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.334607254
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.907961834
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.3197136042
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.1761562541
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3722452829
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.235201969
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3800613265
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.4076172009
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.1648297973
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.1845462457
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.754892853
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2934035921
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.3158163428
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.3575835411
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.2918140978
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.1604647202
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.3304044596
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.34533725
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.2133944262
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.1104784412
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2014621106
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.445750864
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.3078342010
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.630484968
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.4065691542
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.1760984233
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.1783270460
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.3329035945
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.2303724410
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.1103167775
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2201053331
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.1766730620
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.2578088461
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.1130110889
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.3293790604
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.491009858
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.730468175
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.358266216
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.4144428506
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2934005702
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2466251776
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.2302217877
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.4246858410
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2052894496
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.4283973218
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.2931045114
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3506827195
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.3496874791
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.2628629242
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.1701526120
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.2099432788
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1451639178
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.344193002
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.2484878639
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.1862008926
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.1428251204
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.1657134827
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.4120514383
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.3709318785
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.1862823810
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.463424138
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/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.4267868753
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/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.3317366609
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/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.1615028182
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/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3106790346
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3269230669
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/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3221585720



Total test records in report: 2918
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TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.3730886038 Aug 25 06:03:50 PM UTC 24 Aug 25 06:07:20 PM UTC 24 3042680192 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.3365553798 Aug 25 06:05:37 PM UTC 24 Aug 25 06:08:02 PM UTC 24 2599225114 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.1365317217 Aug 25 06:01:44 PM UTC 24 Aug 25 06:09:01 PM UTC 24 3728292358 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.2537489666 Aug 25 06:08:24 PM UTC 24 Aug 25 06:10:04 PM UTC 24 2601683552 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1047033246 Aug 25 06:06:25 PM UTC 24 Aug 25 06:10:21 PM UTC 24 3241445389 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.1115754360 Aug 25 06:05:44 PM UTC 24 Aug 25 06:10:41 PM UTC 24 4760846568 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2855313339 Aug 25 06:07:06 PM UTC 24 Aug 25 06:11:18 PM UTC 24 3861190204 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.3841603586 Aug 25 06:02:42 PM UTC 24 Aug 25 06:11:37 PM UTC 24 5369654878 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.3162045773 Aug 25 06:08:30 PM UTC 24 Aug 25 06:12:05 PM UTC 24 2337832328 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.2676624877 Aug 25 06:08:35 PM UTC 24 Aug 25 06:12:11 PM UTC 24 2694853676 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1051216736 Aug 25 06:08:51 PM UTC 24 Aug 25 06:12:25 PM UTC 24 2529663747 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.360910287 Aug 25 06:10:15 PM UTC 24 Aug 25 06:12:48 PM UTC 24 2661535711 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.2553494860 Aug 25 06:08:22 PM UTC 24 Aug 25 06:13:06 PM UTC 24 3002877588 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3750896884 Aug 25 06:10:57 PM UTC 24 Aug 25 06:13:19 PM UTC 24 2204730762 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.2707117764 Aug 25 06:05:38 PM UTC 24 Aug 25 06:13:49 PM UTC 24 4075226936 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.4100753750 Aug 25 06:09:19 PM UTC 24 Aug 25 06:13:56 PM UTC 24 2525407053 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.3330976304 Aug 25 06:08:53 PM UTC 24 Aug 25 06:14:11 PM UTC 24 2573772764 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.4039947983 Aug 25 06:10:43 PM UTC 24 Aug 25 06:14:20 PM UTC 24 3969073866 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2115187097 Aug 25 06:11:26 PM UTC 24 Aug 25 06:14:28 PM UTC 24 3840384384 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.2378361320 Aug 25 06:08:14 PM UTC 24 Aug 25 06:14:31 PM UTC 24 3583396324 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3709610446 Aug 25 06:09:09 PM UTC 24 Aug 25 06:15:13 PM UTC 24 2545692770 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3569144928 Aug 25 06:10:59 PM UTC 24 Aug 25 06:15:40 PM UTC 24 3621530383 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.3898816874 Aug 25 06:09:02 PM UTC 24 Aug 25 06:15:49 PM UTC 24 3029060586 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.3769520202 Aug 25 06:08:31 PM UTC 24 Aug 25 06:16:06 PM UTC 24 4019088150 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.351661825 Aug 25 06:12:30 PM UTC 24 Aug 25 06:16:41 PM UTC 24 3490823540 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.3496094574 Aug 25 06:08:50 PM UTC 24 Aug 25 06:16:44 PM UTC 24 3541030568 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_vbus.3704549885 Aug 25 06:11:03 PM UTC 24 Aug 25 06:16:56 PM UTC 24 2462862644 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_rand_baudrate.2472213072 Aug 25 06:05:50 PM UTC 24 Aug 25 06:16:58 PM UTC 24 4566022372 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.256660769 Aug 25 06:10:57 PM UTC 24 Aug 25 06:17:27 PM UTC 24 3405990098 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1587070760 Aug 25 06:08:46 PM UTC 24 Aug 25 06:17:48 PM UTC 24 4758696886 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.354009593 Aug 25 06:10:54 PM UTC 24 Aug 25 06:17:57 PM UTC 24 3337014390 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.872879750 Aug 25 06:09:44 PM UTC 24 Aug 25 06:18:08 PM UTC 24 5507510012 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.2765025986 Aug 25 06:08:57 PM UTC 24 Aug 25 06:18:29 PM UTC 24 4139087932 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.452347765 Aug 25 06:08:30 PM UTC 24 Aug 25 06:18:59 PM UTC 24 7418912805 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1853133240 Aug 25 06:11:28 PM UTC 24 Aug 25 06:19:04 PM UTC 24 5565130140 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_entropy.3006984927 Aug 25 06:12:18 PM UTC 24 Aug 25 06:19:19 PM UTC 24 2380373342 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.118334456 Aug 25 06:08:49 PM UTC 24 Aug 25 06:19:31 PM UTC 24 4071760280 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.637683704 Aug 25 06:13:03 PM UTC 24 Aug 25 06:19:50 PM UTC 24 3457642610 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2963631378 Aug 25 06:07:24 PM UTC 24 Aug 25 06:19:52 PM UTC 24 4495520421 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3368180908 Aug 25 06:09:43 PM UTC 24 Aug 25 06:21:02 PM UTC 24 8052154255 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.140703080 Aug 25 06:09:21 PM UTC 24 Aug 25 06:21:08 PM UTC 24 4069314240 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.2458058728 Aug 25 06:10:24 PM UTC 24 Aug 25 06:21:49 PM UTC 24 3774106452 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.335711986 Aug 25 06:14:31 PM UTC 24 Aug 25 06:22:13 PM UTC 24 2971707607 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.122927949 Aug 25 06:10:01 PM UTC 24 Aug 25 06:22:45 PM UTC 24 4295610720 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.308504684 Aug 25 06:09:08 PM UTC 24 Aug 25 06:22:47 PM UTC 24 4208786704 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.912982563 Aug 25 06:10:19 PM UTC 24 Aug 25 06:22:56 PM UTC 24 5446945528 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.101327675 Aug 25 06:15:19 PM UTC 24 Aug 25 06:23:01 PM UTC 24 3227892512 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.1720873924 Aug 25 06:15:15 PM UTC 24 Aug 25 06:23:03 PM UTC 24 4346385580 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.3295778872 Aug 25 06:11:29 PM UTC 24 Aug 25 06:23:26 PM UTC 24 4089879700 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3010032078 Aug 25 06:12:40 PM UTC 24 Aug 25 06:23:29 PM UTC 24 4079216010 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.955776 Aug 25 06:15:16 PM UTC 24 Aug 25 06:24:00 PM UTC 24 3670385500 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.3852236992 Aug 25 06:08:48 PM UTC 24 Aug 25 06:24:04 PM UTC 24 7227727575 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.2269524659 Aug 25 06:08:34 PM UTC 24 Aug 25 06:24:20 PM UTC 24 5246791764 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.3761294035 Aug 25 06:09:21 PM UTC 24 Aug 25 06:24:27 PM UTC 24 4510070568 ps
T676 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.3176216841 Aug 25 06:18:43 PM UTC 24 Aug 25 06:24:53 PM UTC 24 2990301632 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.563852690 Aug 25 06:09:10 PM UTC 24 Aug 25 06:25:42 PM UTC 24 5074717376 ps
T683 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_idle.2087198358 Aug 25 06:19:12 PM UTC 24 Aug 25 06:25:42 PM UTC 24 3595993940 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2122882955 Aug 25 06:15:36 PM UTC 24 Aug 25 06:25:48 PM UTC 24 8102020720 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.3952770775 Aug 25 06:08:35 PM UTC 24 Aug 25 06:25:52 PM UTC 24 10423188398 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.1939566394 Aug 25 06:19:05 PM UTC 24 Aug 25 06:25:55 PM UTC 24 3671591551 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2352623081 Aug 25 06:16:46 PM UTC 24 Aug 25 06:26:02 PM UTC 24 17926180238 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.672274924 Aug 25 06:14:34 PM UTC 24 Aug 25 06:26:20 PM UTC 24 5096061050 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3731629409 Aug 25 06:15:41 PM UTC 24 Aug 25 06:26:33 PM UTC 24 3741776460 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3977382105 Aug 25 06:12:40 PM UTC 24 Aug 25 06:26:38 PM UTC 24 7542631464 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1868409977 Aug 25 06:11:06 PM UTC 24 Aug 25 06:26:46 PM UTC 24 5717262850 ps
T649 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.1020358399 Aug 25 06:19:21 PM UTC 24 Aug 25 06:27:02 PM UTC 24 2507430854 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.3947813578 Aug 25 06:21:41 PM UTC 24 Aug 25 06:27:05 PM UTC 24 3139270010 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.1824136187 Aug 25 06:21:19 PM UTC 24 Aug 25 06:27:14 PM UTC 24 2522990726 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1222006416 Aug 25 06:15:02 PM UTC 24 Aug 25 06:27:35 PM UTC 24 4198953360 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.994887572 Aug 25 06:11:27 PM UTC 24 Aug 25 06:27:35 PM UTC 24 4792879600 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.1903321410 Aug 25 06:17:30 PM UTC 24 Aug 25 06:27:36 PM UTC 24 3593104168 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_entropy.576315242 Aug 25 06:21:42 PM UTC 24 Aug 25 06:27:56 PM UTC 24 3440507328 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.626216310 Aug 25 06:20:40 PM UTC 24 Aug 25 06:28:07 PM UTC 24 3163633414 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.639982526 Aug 25 06:07:25 PM UTC 24 Aug 25 06:28:16 PM UTC 24 5663063458 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3706266460 Aug 25 06:16:15 PM UTC 24 Aug 25 06:28:18 PM UTC 24 4898101338 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.1245080129 Aug 25 06:13:29 PM UTC 24 Aug 25 06:28:19 PM UTC 24 4737621434 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.367360176 Aug 25 06:16:02 PM UTC 24 Aug 25 06:28:45 PM UTC 24 5159114230 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.840079906 Aug 25 06:07:32 PM UTC 24 Aug 25 06:29:00 PM UTC 24 6197630996 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.401375727 Aug 25 06:15:16 PM UTC 24 Aug 25 06:29:07 PM UTC 24 4868740494 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1103939660 Aug 25 06:09:05 PM UTC 24 Aug 25 06:29:29 PM UTC 24 8157306712 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3296280420 Aug 25 06:21:14 PM UTC 24 Aug 25 06:30:35 PM UTC 24 4196406292 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.1541982472 Aug 25 06:20:13 PM UTC 24 Aug 25 06:31:00 PM UTC 24 4963689318 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.3348089086 Aug 25 06:13:44 PM UTC 24 Aug 25 06:32:10 PM UTC 24 4993969572 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc.1165892197 Aug 25 06:25:55 PM UTC 24 Aug 25 06:32:32 PM UTC 24 2857906320 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.2991446232 Aug 25 06:28:31 PM UTC 24 Aug 25 06:32:33 PM UTC 24 2422926856 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.2992334759 Aug 25 06:22:03 PM UTC 24 Aug 25 06:32:41 PM UTC 24 3194466988 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1347984931 Aug 25 06:26:31 PM UTC 24 Aug 25 06:33:10 PM UTC 24 3116585682 ps
T694 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1342248665 Aug 25 06:15:39 PM UTC 24 Aug 25 06:33:16 PM UTC 24 9721044120 ps
T902 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.95430845 Aug 25 06:10:00 PM UTC 24 Aug 25 06:33:20 PM UTC 24 5814549897 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3858018675 Aug 25 06:08:51 PM UTC 24 Aug 25 06:33:40 PM UTC 24 8259887228 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.954697475 Aug 25 06:21:08 PM UTC 24 Aug 25 06:33:56 PM UTC 24 5237096152 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.2538424424 Aug 25 06:08:32 PM UTC 24 Aug 25 06:34:14 PM UTC 24 9772060440 ps
T685 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.2654585639 Aug 25 06:27:57 PM UTC 24 Aug 25 06:34:20 PM UTC 24 3284578368 ps
T903 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access.1937387787 Aug 25 06:11:43 PM UTC 24 Aug 25 06:34:38 PM UTC 24 6001093460 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1565758405 Aug 25 06:24:58 PM UTC 24 Aug 25 06:34:43 PM UTC 24 3872226826 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.510758666 Aug 25 06:30:32 PM UTC 24 Aug 25 06:35:51 PM UTC 24 2466407156 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.2107218446 Aug 25 06:31:06 PM UTC 24 Aug 25 06:36:00 PM UTC 24 2514671241 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.2589378200 Aug 25 06:31:28 PM UTC 24 Aug 25 06:36:16 PM UTC 24 2865286350 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.1410692357 Aug 25 06:22:31 PM UTC 24 Aug 25 06:36:25 PM UTC 24 3757353600 ps
T904 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.755177556 Aug 25 06:30:49 PM UTC 24 Aug 25 06:37:08 PM UTC 24 2554358392 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.524319522 Aug 25 06:19:25 PM UTC 24 Aug 25 06:37:21 PM UTC 24 5570044920 ps
T684 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.966490341 Aug 25 06:14:35 PM UTC 24 Aug 25 06:37:51 PM UTC 24 7003226716 ps
T905 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.3059945147 Aug 25 06:31:44 PM UTC 24 Aug 25 06:37:53 PM UTC 24 2338803600 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_idle.1716680487 Aug 25 06:30:37 PM UTC 24 Aug 25 06:38:07 PM UTC 24 2640475320 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2435382005 Aug 25 06:25:09 PM UTC 24 Aug 25 06:38:41 PM UTC 24 5665116110 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.382322495 Aug 25 06:32:31 PM UTC 24 Aug 25 06:38:44 PM UTC 24 2405475840 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.2737851731 Aug 25 06:19:08 PM UTC 24 Aug 25 06:39:21 PM UTC 24 5497501644 ps
T906 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.2335361008 Aug 25 06:32:03 PM UTC 24 Aug 25 06:39:34 PM UTC 24 2453379800 ps
T907 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.396088048 Aug 25 06:30:37 PM UTC 24 Aug 25 06:39:43 PM UTC 24 3133361254 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.1812938676 Aug 25 06:17:06 PM UTC 24 Aug 25 06:40:13 PM UTC 24 6437731736 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2208003493 Aug 25 06:21:13 PM UTC 24 Aug 25 06:40:19 PM UTC 24 5287104644 ps
T908 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.3940543300 Aug 25 06:35:16 PM UTC 24 Aug 25 06:41:12 PM UTC 24 3185759943 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1999909466 Aug 25 06:32:24 PM UTC 24 Aug 25 06:41:32 PM UTC 24 4702109752 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.285309992 Aug 25 06:30:38 PM UTC 24 Aug 25 06:41:46 PM UTC 24 9245622251 ps
T909 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.814539449 Aug 25 06:31:47 PM UTC 24 Aug 25 06:42:08 PM UTC 24 3505480904 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3025128254 Aug 25 06:08:05 PM UTC 24 Aug 25 06:42:21 PM UTC 24 8912329845 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.913297575 Aug 25 06:08:51 PM UTC 24 Aug 25 06:42:46 PM UTC 24 9755574932 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3632964476 Aug 25 06:30:40 PM UTC 24 Aug 25 06:43:37 PM UTC 24 4206054734 ps
T910 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3125434604 Aug 25 06:32:34 PM UTC 24 Aug 25 06:43:52 PM UTC 24 4718984520 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.2459821043 Aug 25 06:24:57 PM UTC 24 Aug 25 06:44:31 PM UTC 24 6349146520 ps
T911 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3163622603 Aug 25 06:35:08 PM UTC 24 Aug 25 06:44:35 PM UTC 24 3587442296 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.207111778 Aug 25 06:25:56 PM UTC 24 Aug 25 06:44:47 PM UTC 24 5219709908 ps
T912 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1737544405 Aug 25 06:32:31 PM UTC 24 Aug 25 06:45:01 PM UTC 24 4275791882 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2941006609 Aug 25 06:33:29 PM UTC 24 Aug 25 06:45:04 PM UTC 24 7652971949 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.2673006693 Aug 25 06:12:49 PM UTC 24 Aug 25 06:45:12 PM UTC 24 11947333480 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.2403285259 Aug 25 06:40:53 PM UTC 24 Aug 25 06:45:30 PM UTC 24 2434175751 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3374140407 Aug 25 06:37:13 PM UTC 24 Aug 25 06:45:44 PM UTC 24 6777832766 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2737014246 Aug 25 06:32:33 PM UTC 24 Aug 25 06:45:45 PM UTC 24 4617590280 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.2600304510 Aug 25 06:32:49 PM UTC 24 Aug 25 06:45:46 PM UTC 24 3801829710 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3544429193 Aug 25 06:21:17 PM UTC 24 Aug 25 06:46:06 PM UTC 24 9336248152 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.91152876 Aug 25 06:34:41 PM UTC 24 Aug 25 06:46:14 PM UTC 24 3490057032 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.1543696219 Aug 25 06:40:52 PM UTC 24 Aug 25 06:46:20 PM UTC 24 4028866509 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.1902690405 Aug 25 06:37:06 PM UTC 24 Aug 25 06:46:32 PM UTC 24 4733519320 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.887384001 Aug 25 06:31:02 PM UTC 24 Aug 25 06:46:40 PM UTC 24 6322934418 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2431896060 Aug 25 06:10:58 PM UTC 24 Aug 25 06:47:31 PM UTC 24 18406649533 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3366463327 Aug 25 06:35:18 PM UTC 24 Aug 25 06:47:43 PM UTC 24 4390816050 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.2533316707 Aug 25 06:22:02 PM UTC 24 Aug 25 06:47:52 PM UTC 24 5046558930 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3509191171 Aug 25 06:42:33 PM UTC 24 Aug 25 06:47:58 PM UTC 24 3447125849 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2623043348 Aug 25 06:30:47 PM UTC 24 Aug 25 06:48:01 PM UTC 24 5256545168 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3119433771 Aug 25 06:39:00 PM UTC 24 Aug 25 06:48:15 PM UTC 24 5093705336 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2801993995 Aug 25 06:10:44 PM UTC 24 Aug 25 06:48:32 PM UTC 24 9707623814 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_sw_mode.125036302 Aug 25 06:22:55 PM UTC 24 Aug 25 06:49:45 PM UTC 24 5476036830 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4136012993 Aug 25 06:33:57 PM UTC 24 Aug 25 06:48:42 PM UTC 24 4850808624 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.1075323898 Aug 25 06:32:55 PM UTC 24 Aug 25 06:48:48 PM UTC 24 6170142216 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2445777989 Aug 25 06:33:36 PM UTC 24 Aug 25 06:48:48 PM UTC 24 4624517200 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2285845688 Aug 25 06:37:14 PM UTC 24 Aug 25 06:48:50 PM UTC 24 4385444328 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3072324973 Aug 25 06:12:47 PM UTC 24 Aug 25 06:48:51 PM UTC 24 13493185965 ps
T913 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1782199616 Aug 25 06:43:27 PM UTC 24 Aug 25 06:48:54 PM UTC 24 3663066175 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.3616259083 Aug 25 06:39:00 PM UTC 24 Aug 25 06:49:02 PM UTC 24 4822880660 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.1708356620 Aug 25 06:12:19 PM UTC 24 Aug 25 06:49:13 PM UTC 24 8128562790 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2900246115 Aug 25 06:35:07 PM UTC 24 Aug 25 06:49:17 PM UTC 24 5375208700 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3321228066 Aug 25 06:30:53 PM UTC 24 Aug 25 06:49:23 PM UTC 24 7984440016 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4001632834 Aug 25 06:35:06 PM UTC 24 Aug 25 06:49:26 PM UTC 24 4809763148 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2748589378 Aug 25 06:33:58 PM UTC 24 Aug 25 06:49:30 PM UTC 24 3509798200 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2090346415 Aug 25 06:41:52 PM UTC 24 Aug 25 06:49:32 PM UTC 24 2888832624 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.2767667020 Aug 25 06:15:30 PM UTC 24 Aug 25 06:49:59 PM UTC 24 24186745988 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.4041080724 Aug 25 06:40:16 PM UTC 24 Aug 25 06:50:21 PM UTC 24 4432156828 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.975225488 Aug 25 06:43:07 PM UTC 24 Aug 25 06:50:37 PM UTC 24 3241970806 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1304221346 Aug 25 06:34:37 PM UTC 24 Aug 25 06:50:45 PM UTC 24 4204500128 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2022158466 Aug 25 06:40:07 PM UTC 24 Aug 25 06:50:58 PM UTC 24 4964457914 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.1926953070 Aug 25 06:32:19 PM UTC 24 Aug 25 06:51:22 PM UTC 24 4629883692 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.4173686332 Aug 25 06:43:21 PM UTC 24 Aug 25 06:51:23 PM UTC 24 3356473590 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.451672076 Aug 25 06:38:58 PM UTC 24 Aug 25 06:51:29 PM UTC 24 6824851218 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.750772369 Aug 25 06:39:34 PM UTC 24 Aug 25 06:51:38 PM UTC 24 4589803750 ps
T686 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.936067535 Aug 25 06:39:35 PM UTC 24 Aug 25 06:51:42 PM UTC 24 6620518020 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_peri.927437270 Aug 25 06:32:32 PM UTC 24 Aug 25 06:51:44 PM UTC 24 7764131822 ps
T914 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2681193149 Aug 25 06:48:02 PM UTC 24 Aug 25 06:52:40 PM UTC 24 2645725507 ps
T915 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3519806683 Aug 25 06:47:33 PM UTC 24 Aug 25 06:52:54 PM UTC 24 3037140283 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3193436176 Aug 25 06:10:29 PM UTC 24 Aug 25 06:53:31 PM UTC 24 27039201065 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1429231574 Aug 25 06:48:57 PM UTC 24 Aug 25 06:53:33 PM UTC 24 2660089718 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.4026580818 Aug 25 06:32:29 PM UTC 24 Aug 25 06:53:59 PM UTC 24 7998759857 ps
T698 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.1797105208 Aug 25 06:19:49 PM UTC 24 Aug 25 06:54:00 PM UTC 24 8401626868 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.909905999 Aug 25 06:47:36 PM UTC 24 Aug 25 06:54:02 PM UTC 24 4061128264 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.3551188486 Aug 25 06:29:09 PM UTC 24 Aug 25 06:54:16 PM UTC 24 8572405142 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.4272621655 Aug 25 06:32:52 PM UTC 24 Aug 25 06:54:58 PM UTC 24 6523727266 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.657964419 Aug 25 06:08:22 PM UTC 24 Aug 25 06:55:36 PM UTC 24 20193868890 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_crash_alert.1705855364 Aug 25 06:43:10 PM UTC 24 Aug 25 06:56:01 PM UTC 24 5368128424 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.1481183284 Aug 25 06:30:32 PM UTC 24 Aug 25 06:56:05 PM UTC 24 5762732944 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3801740084 Aug 25 06:44:28 PM UTC 24 Aug 25 06:56:34 PM UTC 24 4329777184 ps
T726 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.1345839928 Aug 25 06:37:04 PM UTC 24 Aug 25 06:56:39 PM UTC 24 7815524984 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_scrambling_smoketest.2168938696 Aug 25 06:53:41 PM UTC 24 Aug 25 06:56:55 PM UTC 24 2767280480 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation.1621207069 Aug 25 06:32:35 PM UTC 24 Aug 25 06:57:56 PM UTC 24 6698167952 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2881358270 Aug 25 06:11:30 PM UTC 24 Aug 25 06:57:58 PM UTC 24 22187543516 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.1283683415 Aug 25 06:48:02 PM UTC 24 Aug 25 06:58:50 PM UTC 24 4166239528 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.2383259477 Aug 25 06:25:57 PM UTC 24 Aug 25 06:59:27 PM UTC 24 8555277272 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.2926895692 Aug 25 06:34:59 PM UTC 24 Aug 25 07:00:17 PM UTC 24 12308207985 ps
T916 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.704660720 Aug 25 06:31:03 PM UTC 24 Aug 25 07:00:25 PM UTC 24 7534415436 ps
T917 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3211023599 Aug 25 06:44:34 PM UTC 24 Aug 25 07:00:33 PM UTC 24 7546657341 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.4171198919 Aug 25 06:59:31 PM UTC 24 Aug 25 07:01:21 PM UTC 24 2274420147 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.403891867 Aug 25 06:21:28 PM UTC 24 Aug 25 07:02:18 PM UTC 24 8157855380 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.2173505798 Aug 25 06:35:06 PM UTC 24 Aug 25 07:02:28 PM UTC 24 14052536185 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3531441722 Aug 25 06:38:03 PM UTC 24 Aug 25 07:05:23 PM UTC 24 23489008856 ps
T918 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_smoketest.544119154 Aug 25 07:00:19 PM UTC 24 Aug 25 07:06:10 PM UTC 24 3414293408 ps
T919 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_smoketest.483466908 Aug 25 07:01:39 PM UTC 24 Aug 25 07:07:23 PM UTC 24 2605305400 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1171204399 Aug 25 06:38:02 PM UTC 24 Aug 25 07:07:35 PM UTC 24 22094607608 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1487819063 Aug 25 06:48:06 PM UTC 24 Aug 25 07:07:42 PM UTC 24 9246772648 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_raw_unlock.3752894016 Aug 25 07:03:35 PM UTC 24 Aug 25 07:08:41 PM UTC 24 4144505232 ps
T920 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_smoketest.4180737039 Aug 25 07:05:14 PM UTC 24 Aug 25 07:09:27 PM UTC 24 2650907300 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio_smoketest.1528843403 Aug 25 07:04:45 PM UTC 24 Aug 25 07:10:54 PM UTC 24 2524520162 ps
T921 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_keymgr_functest.7935329 Aug 25 07:00:17 PM UTC 24 Aug 25 07:11:17 PM UTC 24 5491617028 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2329162222 Aug 25 06:30:32 PM UTC 24 Aug 25 07:11:45 PM UTC 24 9080464932 ps
T922 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_smoketest.1875901248 Aug 25 07:05:15 PM UTC 24 Aug 25 07:12:08 PM UTC 24 2479019240 ps
T923 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_smoketest.4162448289 Aug 25 07:04:35 PM UTC 24 Aug 25 07:13:27 PM UTC 24 3362889608 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_plic_smoketest.877086129 Aug 25 07:08:40 PM UTC 24 Aug 25 07:13:40 PM UTC 24 3247638408 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_smoketest.2173808893 Aug 25 07:09:23 PM UTC 24 Aug 25 07:13:51 PM UTC 24 2716151512 ps
T924 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_smoketest.2542886 Aug 25 07:07:35 PM UTC 24 Aug 25 07:15:24 PM UTC 24 3214388392 ps
T925 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_rom.2732888947 Aug 25 07:12:40 PM UTC 24 Aug 25 07:15:57 PM UTC 24 3001572280 ps
T926 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_smoketest.2429991949 Aug 25 07:10:08 PM UTC 24 Aug 25 07:16:13 PM UTC 24 3283133800 ps
T927 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_smoketest.2660506571 Aug 25 07:04:47 PM UTC 24 Aug 25 07:16:14 PM UTC 24 3240077320 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.56236926 Aug 25 07:33:19 PM UTC 24 Aug 25 07:42:17 PM UTC 24 3895606992 ps
T928 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_smoketest.3196553767 Aug 25 07:07:16 PM UTC 24 Aug 25 07:16:33 PM UTC 24 2742248440 ps
T929 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_flash.2907680737 Aug 25 07:12:26 PM UTC 24 Aug 25 07:16:46 PM UTC 24 2145479990 ps
T930 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1010719140 Aug 25 06:55:45 PM UTC 24 Aug 25 07:16:55 PM UTC 24 5201884438 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3474464551 Aug 25 07:02:01 PM UTC 24 Aug 25 07:17:29 PM UTC 24 4817455595 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.3938982361 Aug 25 06:40:14 PM UTC 24 Aug 25 07:18:03 PM UTC 24 17708417183 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3038141165 Aug 25 07:08:41 PM UTC 24 Aug 25 07:18:41 PM UTC 24 4979229352 ps
T931 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_smoketest.2201804381 Aug 25 07:11:35 PM UTC 24 Aug 25 07:18:55 PM UTC 24 3276459154 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.3284388207 Aug 25 06:12:27 PM UTC 24 Aug 25 07:19:10 PM UTC 24 11365465360 ps
T932 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_concurrency.2058792231 Aug 25 07:14:38 PM UTC 24 Aug 25 07:19:30 PM UTC 24 2962851480 ps
T933 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_smoketest.3965376108 Aug 25 07:08:30 PM UTC 24 Aug 25 07:19:32 PM UTC 24 4831056850 ps
T934 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_smoketest.1346993881 Aug 25 07:11:59 PM UTC 24 Aug 25 07:19:55 PM UTC 24 3527904504 ps
T935 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_manufacturer.398578810 Aug 25 07:14:33 PM UTC 24 Aug 25 07:20:08 PM UTC 24 2592588530 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.1072282869 Aug 25 06:46:34 PM UTC 24 Aug 25 07:21:47 PM UTC 24 20198343182 ps
T936 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sival_flash_info_access.1627997457 Aug 25 07:14:38 PM UTC 24 Aug 25 07:21:54 PM UTC 24 3814767912 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3795063358 Aug 25 07:17:58 PM UTC 24 Aug 25 07:23:54 PM UTC 24 3026072943 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2998507605 Aug 25 06:30:51 PM UTC 24 Aug 25 07:23:55 PM UTC 24 12688992181 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.2953861360 Aug 25 07:17:51 PM UTC 24 Aug 25 07:24:02 PM UTC 24 3292126180 ps
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T57 /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_rma.2459293168 Aug 25 06:59:09 PM UTC 24 Aug 25 07:41:54 PM UTC 24 12244253453 ps
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