Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	149336	1			T94	4		T95	6		T96	10
values[2]	4317	1			T556	1		T575	1		T462	6
values[3]	2241	1			T434	8		T854	1		T611	1
values[4]	1612	1			T434	12		T601	41		T531	29
values[5]	1219	1			T434	14		T601	32		T531	23
values[6]	1033	1			T434	19		T601	32		T531	18
values[7]	994	1			T434	27		T601	18		T531	48
values[8]	945	1			T434	25		T601	25		T531	59
values[9]	815	1			T434	21		T601	15		T531	47
values[10]	702	1			T434	50		T601	17		T531	32
values[11]	663	1			T434	83		T601	7		T531	28
values[12]	577	1			T434	59		T601	7		T531	16
values[13]	568	1			T434	53		T601	10		T531	4
values[14]	534	1			T434	42		T601	6		T531	10
values[15]	439	1			T434	44		T601	4		T531	15
values[16]	416	1			T434	47		T601	4		T531	19
values[17]	376	1			T434	63		T601	20		T531	13
values[18]	356	1			T434	76		T601	10		T531	3
values[19]	354	1			T434	55		T601	2		T846	1
values[20]	359	1			T434	46		T601	2		T846	1
values[21]	365	1			T434	49		T601	7		T846	1
values[22]	310	1			T434	27		T601	19		T846	1
values[23]	275	1			T434	26		T601	21		T846	1
values[24]	274	1			T434	24		T601	16		T846	1
values[25]	244	1			T434	18		T601	11		T846	1
values[26]	235	1			T434	13		T601	10		T846	1
values[27]	219	1			T434	10		T846	1		T472	1
values[28]	213	1			T434	12		T846	1		T472	3
values[29]	199	1			T434	7		T846	1		T472	1
values[30]	175	1			T434	3		T846	1		T472	3
values[31]	176	1			T434	6		T846	1		T472	2
values[32]	138	1			T846	1		T472	3		T541	1
values[33]	126	1			T846	1		T472	2		T541	1
values[34]	121	1			T846	1		T472	1		T541	1
values[35]	156	1			T846	1		T472	4		T541	1
values[36]	180	1			T846	1		T472	2		T541	1
values[37]	151	1			T846	1		T472	3		T541	1
values[38]	139	1			T846	1		T472	4		T541	1
values[39]	102	1			T846	1		T472	1		T541	1
values[40]	96	1			T846	1		T472	1		T541	1
values[41]	66	1			T846	1		T472	5		T541	1
values[42]	49	1			T846	1		T472	2		T541	1
values[43]	51	1			T846	1		T472	2		T541	1
values[44]	44	1			T846	2		T472	3		T541	1
values[45]	36	1			T846	1		T472	4		T541	1
values[46]	47	1			T846	1		T472	2		T541	1
values[47]	40	1			T846	1		T472	1		T541	1
values[48]	42	1			T846	1		T472	4		T541	1
values[49]	39	1			T846	1		T472	4		T541	1
values[50]	43	1			T846	1		T472	4		T541	1
values[51]	34	1			T846	1		T472	4		T541	1
values[52]	33	1			T846	1		T472	1		T541	1
values[53]	43	1			T846	1		T472	4		T541	1
values[54]	37	1			T846	1		T472	2		T541	1
values[55]	45	1			T846	1		T472	4		T541	1
values[56]	48	1			T846	1		T472	2		T541	1
values[57]	33	1			T846	1		T472	1		T541	1
values[58]	33	1			T846	1		T472	1		T541	1
values[59]	38	1			T846	1		T472	3		T541	1
values[60]	41	1			T846	1		T472	2		T541	1
values[61]	44	1			T846	1		T472	1		T541	2
values[62]	44	1			T846	1		T472	3		T541	1
values[63]	50	1			T846	1		T472	13		T541	1
values[64]	35	1			T846	1		T472	5		T541	1
values[65]	36	1			T846	1		T472	1		T541	1
values[66]	33	1			T846	1		T472	2		T541	1
values[67]	36	1			T846	1		T472	3		T541	1
values[68]	35	1			T846	1		T472	1		T541	1
values[69]	48	1			T846	1		T472	2		T541	1
values[70]	46	1			T846	1		T472	2		T541	1
values[71]	48	1			T846	1		T472	2		T541	1
values[72]	49	1			T846	1		T472	2		T541	1
values[73]	57	1			T846	1		T472	3		T541	1
values[74]	55	1			T846	1		T472	4		T541	1
values[75]	46	1			T846	1		T472	1		T541	1
values[76]	58	1			T846	1		T472	2		T541	1
values[77]	42	1			T846	1		T472	2		T541	1
values[78]	50	1			T846	1		T472	2		T541	1
values[79]	42	1			T846	1		T472	1		T541	1
values[80]	67	1			T846	1		T472	4		T541	1
values[81]	50	1			T846	1		T472	2		T541	1
values[82]	49	1			T846	1		T472	5		T541	1
values[83]	52	1			T846	6		T472	2		T541	1
values[84]	57	1			T846	6		T472	4		T541	1
values[85]	55	1			T846	3		T472	2		T541	1
values[86]	60	1			T846	2		T472	3		T541	3
values[87]	65	1			T846	3		T472	2		T541	3
values[88]	54	1			T846	1		T472	3		T541	3
values[89]	51	1			T846	2		T472	1		T541	1
values[90]	47	1			T846	2		T472	1		T541	2
values[91]	67	1			T846	1		T472	7		T541	4
values[92]	63	1			T846	3		T472	1		T541	8
values[93]	57	1			T846	3		T472	2		T541	4
values[94]	62	1			T846	1		T472	2		T541	2
values[95]	67	1			T846	3		T472	5		T541	3
values[96]	54	1			T846	6		T472	2		T541	3
values[97]	56	1			T846	3		T472	4		T541	4
values[98]	48	1			T846	3		T472	1		T541	1
values[99]	53	1			T846	4		T472	1		T541	3
values[100]	81	1			T846	10		T472	2		T541	3
values[101]	76	1			T846	1		T472	5		T541	1
values[102]	66	1			T846	2		T472	4		T541	2
values[103]	62	1			T846	2		T472	1		T541	6
values[104]	51	1			T846	2		T472	2		T541	5
values[105]	53	1			T846	4		T472	1		T541	2
values[106]	70	1			T846	2		T472	2		T541	7
values[107]	56	1			T846	2		T472	2		T541	1
values[108]	62	1			T846	1		T472	4		T541	1
values[109]	63	1			T846	4		T472	9		T541	1
values[110]	56	1			T846	2		T472	3		T541	2
values[111]	59	1			T846	2		T472	1		T541	1
values[112]	68	1			T846	2		T472	2		T541	1
values[113]	64	1			T846	1		T472	2		T541	4
values[114]	61	1			T846	3		T472	3		T541	1
values[115]	68	1			T846	2		T472	4		T541	3
values[116]	63	1			T846	2		T472	4		T541	2
values[117]	61	1			T846	4		T472	3		T541	1
values[118]	45	1			T846	2		T472	2		T541	1
values[119]	58	1			T846	3		T472	1		T541	1
values[120]	63	1			T846	2		T472	3		T541	3
values[121]	68	1			T846	1		T472	3		T541	2
values[122]	63	1			T846	2		T472	5		T541	2
values[123]	103	1			T846	1		T472	10		T541	4
values[124]	160	1			T846	3		T472	24		T541	1
values[125]	337	1			T846	1		T472	55		T541	3
values[126]	733	1			T846	10		T472	75		T541	9
values[127]	1653	1			T846	95		T472	33		T541	89
values[128]	2833	1			T846	193		T472	1		T541	209