Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	141343	1			T94	14		T95	3		T96	4
values[2]	11123	1			T247	1		T556	3		T530	4
values[3]	4372	1			T494	21		T658	138		T601	37
values[4]	2382	1			T494	8		T658	57		T601	7
values[5]	1453	1			T494	5		T658	8		T477	17
values[6]	870	1			T494	8		T658	7		T477	4
values[7]	559	1			T494	4		T658	1		T477	7
values[8]	386	1			T494	3		T477	8		T531	7
values[9]	312	1			T494	8		T531	3		T673	6
values[10]	258	1			T494	14		T531	4		T673	4
values[11]	269	1			T494	4		T531	8		T673	21
values[12]	248	1			T494	4		T531	3		T673	5
values[13]	226	1			T494	5		T531	3		T673	5
values[14]	257	1			T494	11		T531	1		T673	9
values[15]	222	1			T494	13		T531	4		T673	7
values[16]	238	1			T494	4		T531	3		T673	4
values[17]	239	1			T494	8		T531	7		T673	10
values[18]	227	1			T494	5		T531	2		T673	7
values[19]	211	1			T494	8		T531	1		T673	13
values[20]	198	1			T494	10		T531	3		T673	14
values[21]	204	1			T494	8		T531	1		T673	5
values[22]	172	1			T494	9		T531	2		T673	5
values[23]	196	1			T494	4		T531	3		T673	7
values[24]	213	1			T494	4		T531	5		T673	19
values[25]	259	1			T494	5		T531	17		T673	9
values[26]	244	1			T494	7		T531	11		T673	7
values[27]	193	1			T494	3		T531	1		T673	5
values[28]	208	1			T494	10		T531	2		T673	10
values[29]	200	1			T494	9		T531	1		T673	4
values[30]	168	1			T494	3		T531	1		T673	4
values[31]	198	1			T494	11		T531	3		T673	10
values[32]	230	1			T494	2		T531	2		T673	8
values[33]	184	1			T531	3		T673	6		T660	1
values[34]	209	1			T531	1		T673	8		T660	1
values[35]	179	1			T531	1		T673	4		T660	4
values[36]	156	1			T531	2		T673	4		T660	1
values[37]	158	1			T531	3		T673	3		T660	2
values[38]	223	1			T531	7		T673	18		T660	2
values[39]	206	1			T531	10		T673	5		T660	3
values[40]	203	1			T531	6		T673	4		T660	4
values[41]	196	1			T531	6		T673	6		T660	1
values[42]	173	1			T531	3		T673	8		T660	1
values[43]	203	1			T531	1		T673	7		T660	3
values[44]	250	1			T531	2		T673	3		T660	1
values[45]	196	1			T531	6		T673	5		T660	2
values[46]	183	1			T531	7		T673	5		T660	1
values[47]	186	1			T531	5		T673	17		T660	1
values[48]	193	1			T531	5		T673	25		T660	2
values[49]	189	1			T531	3		T673	9		T660	4
values[50]	176	1			T531	2		T673	2		T660	8
values[51]	180	1			T531	1		T673	12		T660	3
values[52]	193	1			T531	4		T673	11		T660	7
values[53]	185	1			T531	1		T673	4		T660	9
values[54]	192	1			T531	2		T673	2		T660	10
values[55]	208	1			T531	3		T660	14		T848	1
values[56]	143	1			T531	1		T660	7		T848	1
values[57]	155	1			T531	4		T660	1		T848	1
values[58]	171	1			T531	5		T660	4		T848	1
values[59]	155	1			T531	10		T848	1		T627	10
values[60]	153	1			T531	4		T848	1		T627	9
values[61]	131	1			T531	2		T848	1		T627	3
values[62]	133	1			T531	3		T848	1		T627	11
values[63]	141	1			T531	14		T848	1		T627	2
values[64]	151	1			T531	21		T848	1		T627	3
values[65]	119	1			T531	14		T848	1		T627	5
values[66]	96	1			T531	4		T848	1		T627	9
values[67]	128	1			T531	8		T848	1		T627	10
values[68]	103	1			T531	7		T848	1		T627	4
values[69]	90	1			T531	13		T848	1		T627	3
values[70]	98	1			T531	6		T848	1		T823	1
values[71]	82	1			T531	9		T848	1		T823	1
values[72]	83	1			T531	14		T848	1		T823	1
values[73]	90	1			T531	11		T848	1		T823	1
values[74]	75	1			T531	10		T848	1		T823	1
values[75]	67	1			T848	1		T823	1		T830	1
values[76]	59	1			T848	1		T823	1		T830	1
values[77]	64	1			T848	1		T823	1		T830	1
values[78]	55	1			T848	1		T823	2		T830	1
values[79]	44	1			T848	1		T823	1		T830	1
values[80]	56	1			T848	1		T823	1		T830	1
values[81]	56	1			T848	1		T823	1		T830	2
values[82]	46	1			T848	1		T823	1		T830	1
values[83]	33	1			T848	1		T823	1		T830	1
values[84]	62	1			T848	1		T823	7		T830	1
values[85]	39	1			T848	1		T823	5		T830	1
values[86]	41	1			T848	1		T823	3		T830	1
values[87]	36	1			T848	1		T823	1		T830	1
values[88]	43	1			T848	1		T823	1		T830	1
values[89]	37	1			T848	1		T823	5		T830	1
values[90]	32	1			T848	1		T823	1		T830	1
values[91]	41	1			T848	1		T823	4		T830	1
values[92]	46	1			T848	1		T823	4		T830	3
values[93]	36	1			T848	1		T823	2		T830	1
values[94]	40	1			T848	1		T823	6		T830	2
values[95]	38	1			T848	1		T823	2		T830	1
values[96]	46	1			T848	1		T823	3		T830	1
values[97]	51	1			T848	1		T823	3		T830	2
values[98]	65	1			T848	1		T823	2		T830	1
values[99]	45	1			T848	1		T823	1		T830	1
values[100]	48	1			T848	2		T823	2		T830	1
values[101]	50	1			T848	3		T823	3		T830	1
values[102]	43	1			T848	1		T823	1		T830	3
values[103]	49	1			T848	2		T823	1		T830	3
values[104]	47	1			T848	3		T823	2		T830	3
values[105]	41	1			T848	1		T823	1		T830	2
values[106]	39	1			T848	5		T823	1		T830	1
values[107]	40	1			T848	1		T823	2		T830	4
values[108]	39	1			T848	1		T823	2		T830	2
values[109]	39	1			T848	1		T823	3		T830	1
values[110]	43	1			T848	3		T823	5		T830	1
values[111]	45	1			T848	1		T823	3		T830	2
values[112]	42	1			T848	3		T823	1		T830	2
values[113]	37	1			T848	1		T823	2		T830	2
values[114]	46	1			T848	5		T823	7		T830	4
values[115]	63	1			T848	3		T823	2		T830	2
values[116]	41	1			T848	1		T823	3		T830	2
values[117]	50	1			T848	1		T823	2		T830	5
values[118]	46	1			T848	2		T823	2		T830	2
values[119]	32	1			T848	2		T823	1		T830	2
values[120]	37	1			T848	3		T823	1		T830	1
values[121]	38	1			T848	2		T823	2		T830	3
values[122]	33	1			T848	3		T823	1		T830	2
values[123]	29	1			T848	1		T823	3		T830	2
values[124]	36	1			T848	4		T823	2		T830	1
values[125]	40	1			T848	1		T823	1		T830	1
values[126]	84	1			T848	2		T823	3		T830	5
values[127]	579	1			T848	32		T823	24		T830	30
values[128]	4872	1			T848	328		T823	266		T830	335