Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	151610	1			T95	4		T96	3		T99	3
values[2]	4368	1			T427	65		T556	1		T530	2
values[3]	1971	1			T427	45		T669	46		T543	50
values[4]	1555	1			T427	50		T669	37		T543	22
values[5]	1356	1			T427	30		T669	41		T543	17
values[6]	1211	1			T427	17		T669	31		T543	1
values[7]	984	1			T427	21		T669	22		T601	3
values[8]	833	1			T427	4		T669	18		T601	7
values[9]	699	1			T427	4		T669	14		T601	2
values[10]	630	1			T427	3		T669	13		T601	2
values[11]	513	1			T427	7		T669	12		T601	1
values[12]	536	1			T427	8		T669	19		T601	2
values[13]	460	1			T427	7		T669	25		T601	3
values[14]	518	1			T427	10		T669	23		T601	2
values[15]	463	1			T427	8		T669	11		T522	1
values[16]	416	1			T427	14		T669	7		T522	1
values[17]	414	1			T427	14		T669	9		T522	1
values[18]	334	1			T427	19		T669	24		T522	1
values[19]	281	1			T427	39		T669	13		T522	1
values[20]	314	1			T427	38		T669	2		T522	1
values[21]	284	1			T427	27		T522	1		T812	1
values[22]	273	1			T427	16		T522	1		T812	1
values[23]	203	1			T522	1		T812	1		T831	16
values[24]	182	1			T522	1		T812	1		T831	2
values[25]	168	1			T522	1		T812	1		T529	11
values[26]	166	1			T522	1		T812	1		T529	6
values[27]	163	1			T522	1		T812	1		T529	8
values[28]	171	1			T522	1		T812	1		T529	14
values[29]	159	1			T522	1		T812	1		T529	6
values[30]	158	1			T522	1		T812	1		T529	8
values[31]	161	1			T522	1		T812	1		T529	14
values[32]	144	1			T522	1		T812	1		T529	12
values[33]	132	1			T522	1		T812	1		T529	2
values[34]	138	1			T522	1		T812	1		T529	5
values[35]	131	1			T522	1		T812	1		T529	4
values[36]	139	1			T522	1		T812	1		T529	2
values[37]	103	1			T522	1		T812	1		T529	2
values[38]	102	1			T522	1		T812	1		T529	2
values[39]	100	1			T522	1		T812	1		T835	1
values[40]	106	1			T522	1		T812	1		T835	1
values[41]	111	1			T522	1		T812	1		T835	1
values[42]	121	1			T522	1		T812	1		T835	1
values[43]	131	1			T522	1		T812	1		T835	1
values[44]	113	1			T522	1		T812	1		T835	1
values[45]	70	1			T522	1		T812	1		T835	1
values[46]	78	1			T522	1		T812	1		T835	1
values[47]	73	1			T522	1		T812	1		T835	1
values[48]	60	1			T522	1		T812	1		T835	1
values[49]	65	1			T522	1		T812	1		T835	1
values[50]	58	1			T522	2		T812	1		T835	1
values[51]	60	1			T522	1		T812	1		T835	1
values[52]	56	1			T522	1		T812	1		T835	1
values[53]	58	1			T522	1		T812	1		T835	1
values[54]	59	1			T522	1		T812	1		T835	1
values[55]	58	1			T522	1		T812	1		T835	1
values[56]	74	1			T522	1		T812	1		T835	1
values[57]	67	1			T522	1		T812	1		T835	1
values[58]	51	1			T522	1		T812	2		T835	1
values[59]	65	1			T522	1		T812	1		T835	1
values[60]	60	1			T522	1		T812	1		T835	1
values[61]	66	1			T522	1		T812	1		T835	1
values[62]	61	1			T522	1		T812	1		T835	1
values[63]	65	1			T522	1		T812	1		T835	1
values[64]	62	1			T522	1		T812	1		T835	1
values[65]	62	1			T522	1		T812	1		T835	1
values[66]	57	1			T522	1		T812	1		T835	1
values[67]	63	1			T522	1		T812	1		T835	1
values[68]	61	1			T522	1		T812	1		T835	1
values[69]	54	1			T522	1		T812	1		T835	1
values[70]	56	1			T522	1		T812	1		T835	1
values[71]	73	1			T522	1		T812	1		T835	1
values[72]	71	1			T522	1		T812	1		T835	1
values[73]	54	1			T522	1		T812	1		T835	1
values[74]	54	1			T522	1		T812	1		T835	1
values[75]	69	1			T522	1		T812	1		T835	2
values[76]	68	1			T522	1		T812	1		T835	1
values[77]	66	1			T522	1		T812	1		T835	1
values[78]	69	1			T522	1		T812	1		T835	1
values[79]	67	1			T522	1		T812	1		T835	1
values[80]	70	1			T522	1		T812	1		T835	1
values[81]	70	1			T522	1		T812	1		T835	1
values[82]	79	1			T522	1		T812	1		T835	1
values[83]	96	1			T522	1		T812	1		T835	1
values[84]	92	1			T522	1		T812	1		T835	1
values[85]	77	1			T522	1		T812	1		T835	1
values[86]	76	1			T522	1		T812	1		T835	1
values[87]	86	1			T522	1		T812	1		T835	1
values[88]	103	1			T522	1		T812	1		T835	1
values[89]	96	1			T522	1		T812	1		T835	1
values[90]	94	1			T522	1		T812	1		T835	1
values[91]	84	1			T522	1		T812	1		T835	1
values[92]	95	1			T522	1		T812	1		T835	1
values[93]	81	1			T522	1		T812	4		T835	1
values[94]	84	1			T522	1		T812	4		T835	1
values[95]	77	1			T522	1		T812	2		T835	1
values[96]	85	1			T522	1		T812	3		T835	1
values[97]	105	1			T522	1		T812	3		T835	1
values[98]	94	1			T522	1		T812	1		T835	1
values[99]	107	1			T522	2		T812	1		T835	1
values[100]	109	1			T522	1		T812	2		T835	2
values[101]	79	1			T522	1		T812	1		T835	2
values[102]	113	1			T522	1		T812	5		T835	6
values[103]	115	1			T522	5		T812	1		T835	5
values[104]	102	1			T522	6		T812	1		T835	2
values[105]	100	1			T522	1		T812	3		T835	3
values[106]	118	1			T522	4		T812	2		T835	7
values[107]	105	1			T522	4		T812	4		T835	2
values[108]	95	1			T522	2		T812	4		T835	1
values[109]	114	1			T522	5		T812	1		T835	5
values[110]	100	1			T522	3		T812	1		T835	3
values[111]	106	1			T522	4		T812	2		T835	2
values[112]	103	1			T522	1		T812	4		T835	4
values[113]	123	1			T522	2		T812	3		T835	4
values[114]	130	1			T522	1		T812	2		T835	4
values[115]	107	1			T522	2		T812	2		T835	2
values[116]	104	1			T522	1		T812	3		T835	2
values[117]	110	1			T522	1		T812	1		T835	4
values[118]	99	1			T522	2		T812	1		T835	1
values[119]	133	1			T522	2		T812	2		T835	3
values[120]	126	1			T522	2		T812	4		T835	1
values[121]	103	1			T522	2		T812	2		T835	1
values[122]	115	1			T522	2		T812	2		T835	2
values[123]	138	1			T522	1		T812	1		T835	4
values[124]	199	1			T522	1		T812	1		T835	2
values[125]	359	1			T522	2		T812	1		T835	2
values[126]	967	1			T522	19		T812	17		T835	7
values[127]	3475	1			T522	135		T812	105		T835	92
values[128]	5736	1			T522	271		T812	149		T835	176