Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	429	1			T570	4		T434	2		T695	3
all_values[1]	442	1			T561	1		T570	2		T514	1
all_values[2]	518	1			T427	1		T561	1		T570	3
all_values[3]	471	1			T669	1		T561	1		T570	5
all_values[4]	466	1			T669	1		T570	2		T578	1
all_values[5]	488	1			T427	1		T572	1		T570	2
all_values[6]	552	1			T573	1		T570	4		T494	1
all_values[7]	527	1			T561	1		T570	2		T494	1
all_values[8]	472	1			T570	2		T695	4		T658	1
all_values[9]	469	1			T573	1		T561	1		T543	1
all_values[10]	467	1			T573	1		T570	5		T695	3
all_values[11]	461	1			T579	1		T543	1		T570	4
all_values[12]	479	1			T570	6		T494	1		T514	1
all_values[13]	478	1			T669	1		T573	1		T543	1
all_values[14]	471	1			T427	1		T572	1		T570	3
all_values[15]	459	1			T570	1		T494	1		T695	1
all_values[16]	474	1			T427	1		T669	1		T543	1
all_values[17]	496	1			T669	1		T573	1		T561	1
all_values[18]	452	1			T561	2		T570	5		T695	1
all_values[19]	507	1			T561	1		T570	2		T695	2
all_values[20]	465	1			T669	1		T573	1		T561	1
all_values[21]	497	1			T579	1		T561	2		T570	5
all_values[22]	506	1			T669	1		T570	4		T434	1
all_values[23]	490	1			T427	1		T669	1		T561	3
all_values[24]	485	1			T570	3		T434	1		T695	2
all_values[25]	469	1			T427	1		T573	1		T570	4
all_values[26]	490	1			T570	5		T514	1		T695	2
all_values[27]	494	1			T286	1		T669	1		T570	2
all_values[28]	459	1			T669	1		T561	3		T543	1
all_values[29]	488	1			T570	1		T578	1		T514	1
all_values[30]	496	1			T570	4		T695	1		T671	1
all_values[31]	490	1			T669	1		T573	1		T570	4
all_values[32]	470	1			T561	2		T543	1		T570	3
all_values[33]	448	1			T570	1		T671	1		T658	2
all_values[34]	456	1			T561	1		T543	1		T572	1
all_values[35]	487	1			T669	2		T573	1		T561	1
all_values[36]	473	1			T570	2		T695	3		T611	4
all_values[37]	492	1			T579	1		T561	2		T572	1
all_values[38]	482	1			T427	1		T561	1		T570	4
all_values[39]	467	1			T570	2		T695	2		T671	1
all_values[40]	474	1			T572	1		T570	6		T695	3
all_values[41]	438	1			T669	2		T570	2		T494	1
all_values[42]	480	1			T579	1		T561	1		T570	3
all_values[43]	466	1			T572	1		T570	3		T578	1
all_values[44]	460	1			T561	1		T570	4		T494	1
all_values[45]	479	1			T561	1		T570	4		T494	1
all_values[46]	483	1			T573	2		T543	1		T570	5
all_values[47]	524	1			T573	1		T561	1		T570	1
all_values[48]	479	1			T573	1		T561	1		T572	1
all_values[49]	492	1			T579	1		T572	1		T570	5