Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3655	1			T554	2		T489	3		T566	1
all_values[1]	3648	1			T554	1		T489	2		T561	8
all_values[2]	3541	1			T554	1		T489	1		T561	9
all_values[3]	3709	1			T554	3		T489	2		T566	1
all_values[4]	3650	1			T489	1		T561	10		T570	17
all_values[5]	3583	1			T554	3		T489	1		T561	12
all_values[6]	3692	1			T554	1		T489	1		T566	1
all_values[7]	3576	1			T554	2		T489	3		T561	10
all_values[8]	3689	1			T554	1		T489	1		T566	1
all_values[9]	3646	1			T554	1		T489	2		T566	1
all_values[10]	3628	1			T489	2		T561	16		T570	22
all_values[11]	3609	1			T554	2		T489	4		T561	12
all_values[12]	3549	1			T554	2		T489	3		T561	10
all_values[13]	3734	1			T554	2		T489	1		T566	2
all_values[14]	3501	1			T554	1		T489	4		T561	12
all_values[15]	3707	1			T554	1		T489	2		T566	2
all_values[16]	3704	1			T561	12		T570	24		T576	4
all_values[17]	3668	1			T554	2		T489	1		T566	1
all_values[18]	3585	1			T554	2		T561	10		T570	22
all_values[19]	3679	1			T554	1		T489	1		T566	3
all_values[20]	3569	1			T554	1		T489	2		T561	6
all_values[21]	3670	1			T554	2		T489	1		T566	2
all_values[22]	3642	1			T554	1		T489	1		T566	3
all_values[23]	3683	1			T554	2		T489	4		T561	9
all_values[24]	3725	1			T554	1		T489	4		T566	1
all_values[25]	3704	1			T489	3		T566	4		T561	9
all_values[26]	3787	1			T554	1		T489	3		T566	1
all_values[27]	3723	1			T554	1		T566	1		T561	13
all_values[28]	3688	1			T554	1		T489	2		T561	15
all_values[29]	3612	1			T554	2		T561	17		T570	25
all_values[30]	3601	1			T561	19		T570	20		T494	9
all_values[31]	3656	1			T554	2		T489	3		T561	13
all_values[32]	3685	1			T554	1		T489	6		T566	1
all_values[33]	3636	1			T554	2		T489	3		T566	1
all_values[34]	3633	1			T554	3		T489	2		T566	1
all_values[35]	3609	1			T554	1		T489	3		T561	11
all_values[36]	3691	1			T489	1		T566	1		T561	17
all_values[37]	3605	1			T554	1		T489	1		T566	1
all_values[38]	3617	1			T554	2		T561	11		T570	23
all_values[39]	3661	1			T554	1		T489	4		T561	10
all_values[40]	3633	1			T489	2		T566	2		T561	12
all_values[41]	3646	1			T554	1		T489	3		T566	1
all_values[42]	3611	1			T489	2		T566	1		T561	18
all_values[43]	3597	1			T554	1		T489	1		T566	1
all_values[44]	3674	1			T566	3		T561	13		T570	20
all_values[45]	3630	1			T489	5		T566	1		T561	11
all_values[46]	3491	1			T489	1		T566	1		T561	17
all_values[47]	3750	1			T554	1		T566	2		T561	14
all_values[48]	3589	1			T489	4		T566	1		T561	17
all_values[49]	3661	1			T554	2		T489	1		T561	15
all_values[50]	3673	1			T554	3		T489	3		T566	1
all_values[51]	3671	1			T554	1		T489	1		T561	5
all_values[52]	3810	1			T554	3		T489	1		T566	1
all_values[53]	3516	1			T566	3		T561	23		T570	18
all_values[54]	3595	1			T489	1		T561	16		T570	16
all_values[55]	3472	1			T489	3		T561	13		T570	20
all_values[56]	3729	1			T489	4		T566	5		T561	13
all_values[57]	3665	1			T554	1		T489	2		T566	1
all_values[58]	3679	1			T489	4		T561	12		T570	30
all_values[59]	3579	1			T554	1		T489	1		T561	14
all_values[60]	3582	1			T489	3		T566	1		T561	14
all_values[61]	3614	1			T554	1		T489	4		T561	16
all_values[62]	3660	1			T489	2		T561	16		T570	19
all_values[63]	3721	1			T489	2		T566	1		T561	11