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 LINE       1298
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T76,T249,T457
1	0	1	Covered	T83,T84,T280
1	1	0	Covered	T398,T671,T477
1	1	1	Covered	T82,T83,T84

 LINE       1303
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T82,T83,T84
1	0	1	Covered	T83,T84,T280
1	1	0	Covered	T543,T398,T487
1	1	1	Covered	T457,T72,T137

 LINE       1308
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T82,T83,T84
1	0	1	Covered	T280,T277,T306
1	1	0	Covered	T669,T543,T398
1	1	1	Covered	T71,T530,T462

 LINE       1317
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T71,T554,T669
1	1	0	Covered	T672
1	1	1	Covered	T6,T4,T5

 LINE       1318
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T71,T465,T556
1	1	0	Covered	T673,T674
1	1	1	Covered	T6,T4,T5

 LINE       1319
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T4,T5
1	0	1	Covered	T71,T463,T563
1	1	0	Covered	T675
1	1	1	Covered	T1,T2,T3