Go
back
71 if (offset < NumSrc) begin : gen_assign
72 185/186 ==> assign vld_tree[Pa] = valid_i[offset];
Tests: T127 T128 T331 | T127 T128 T331 | T127 T128 T331 | T127 T128 T331 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T127 T128 T331 | T130 T131 T331 | T130 T131 T331 | T130 T131 T331 | T130 T131 T331 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T130 T131 T331 | T3 T65 T331 | T3 T65 T331 | T3 T65 T331 | T3 T65 T331 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T3 T65 T331 | T37 T331 T66 | T37 T331 T66 | T37 T331 T66 | T37 T331 T66 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T37 T331 T66 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T11 T123 T229 | T123 T191 T192 | T123 T191 T192 | T123 T191 T192 | T123 T191 T192 | T14 T123 T50 | T123 T191 T192 | T123 T191 T192 | T5 T334 T60 | T5 T334 T60 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T5 T334 T60 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T61 T334 T62 | T61 T334 T62 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T61 T334 T62 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T64 T334 T139 | T64 T334 T139 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T63 T64 T334 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T123 T135 T191 | T29 T123 T191 | T123 T191 T192 | T123 T191 T192 | T123 T191 T192 | T245 T193 T337 | T84 T293 T280 | T338 T334 T277 | T82 T83 T193 | T123 T191 T192 | T123 T191 T192 | T123 T191 T192 | T123 T191 T192 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T4 T13 T292 | T68 T331 T237 | T140 T334 T141 | T339 T272 T324 | T271 T272 T193 | T178 T123 T340 | T123 T191 T192 | T118 T146 T341 | T118 T146 T341 | T146 T341 T334 | T146 T341 T334 | T118 T146 T341 | T334 T335 T336 | T294 T342 T343 | T334 T335 T336 | T334 T335 T336 | T123 T191 T192 | T123 T191 T192 | T123 T191 T192 | T344 T123 T182 | T123 T191 T192 | T334 T335 T336 | T334 T345 T346 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T345 T346 | T334 T335 T336 | T334 T345 T346 | T334 T335 T336
73 assign idx_tree[Pa] = offset;
74 186/186 assign max_tree[Pa] = values_i[offset];
Tests: T287 T35 T347 | T127 T128 T287 | T127 T128 T287 | T127 T128 T287 | T127 T128 T287 | T127 T128 T287 | T127 T128 T287 | T127 T128 T287 | T127 T128 T287 | T127 T128 T287 | T130 T131 T287 | T130 T131 T287 | T130 T131 T287 | T130 T131 T287 | T130 T131 T287 | T130 T131 T287 | T130 T131 T287 | T130 T131 T287 | T130 T131 T287 | T3 T287 T65 | T3 T287 T65 | T3 T287 T65 | T3 T287 T65 | T3 T287 T65 | T3 T287 T65 | T3 T287 T65 | T3 T287 T65 | T3 T287 T65 | T37 T287 T123 | T37 T287 T123 | T37 T287 T123 | T37 T287 T123 | T37 T287 T123 | T37 T287 T123 | T37 T287 T123 | T37 T287 T123 | T37 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T14 T11 | T14 T287 T123 | T14 T287 T123 | T14 T11 T12 | T14 T11 T12 | T14 T287 T123 | T287 T123 T331 | T287 T123 T331 | T5 T287 T123 | T5 T287 T123 | T287 T123 T331 | T5 T287 T123 | T5 T287 T123 | T5 T287 T123 | T5 T287 T123 | T5 T287 T123 | T287 T123 T331 | T5 T287 T123 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T61 T287 T123 | T61 T287 T123 | T287 T123 T331 | T61 T287 T123 | T61 T287 T123 | T61 T287 T123 | T61 T287 T123 | T61 T287 T123 | T287 T123 T331 | T61 T287 T123 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T64 T287 T123 | T64 T287 T123 | T287 T123 T331 | T64 T287 T123 | T64 T287 T123 | T64 T287 T123 | T64 T287 T123 | T64 T287 T123 | T287 T123 T331 | T63 T64 T287 | T63 T287 T123 | T287 T123 T331 | T63 T287 T123 | T63 T287 T123 | T63 T287 T123 | T29 T287 T123 | T29 T287 T123 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T82 T83 T84 | T82 T83 T84 | T82 T83 T84 | T82 T83 T84 | T11 T12 T287 | T11 T12 T287 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T4 T13 T339 | T68 T287 T123 | T140 T287 T123 | T82 T339 T272 | T271 T82 T272 | T178 T287 T123 | T287 T123 T331 | T118 T146 T341 | T118 T146 T341 | T118 T146 T341 | T118 T146 T341 | T118 T146 T341 | T287 T123 T331 | T294 T342 T287 | T294 T342 T287 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T344 T123 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331
75 end else begin : gen_tie_off
76 assign vld_tree[Pa] = '0;
77 assign idx_tree[Pa] = '0;
78 assign max_tree[Pa] = '0;
79 end
80 // This creates the node assignments.
81 end else begin : gen_nodes
82 logic sel; // Local helper variable
83 // In case only one of the parents is valid, forward that one
84 // In case both parents are valid, forward the one with higher value
85 185/185(70 unreachable) assign sel = (~vld_tree[C0] & vld_tree[C1]) |
Tests: T3 T4 T5 | T3 T5 T29 | T3 T27 T130 | T5 T29 T27 | T4 T118 T13 | T3 T130 T127 | T27 T37 T287 | T5 T27 T14 | T29 T63 T61 | T4 T13 T271 | T118 T146 T341 | T130 T127 T131 | T3 T130 T131 | T27 T37 T287 | T27 T287 T123 | T5 T27 T14 | T5 T61 T287 | T61 T64 T287 | T29 T63 T64 | T82 T83 T84 | T4 T13 T271 | T118 T146 T341 | T287 T123 T331 | T127 T128 T287 | T130 T127 T131 | T3 T130 T131 | T3 T37 T287 | T27 T37 T287 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T11 T287 | T5 T14 T11 | T5 T287 T123 | T61 T287 T123 | T61 T287 T123 | T64 T287 T123 | T63 T64 T287 | T29 T63 T245 | T11 T82 T12 | T287 T123 T331 | T287 T123 T331 | T4 T13 T271 | T118 T146 T341 | T287 T344 T123 | T287 T123 T331 | T127 T128 T287 | T127 T128 T287 | T130 T127 T131 | T130 T131 T287 | T3 T130 T131 | T3 T287 T65 | T3 T287 T65 | T37 T287 T123 | T37 T287 T123 | T27 T37 T287 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T14 T11 | T14 T11 T12 | T5 T287 T123 | T5 T287 T123 | T5 T287 T123 | T287 T123 T331 | T61 T287 T123 | T61 T287 T123 | T61 T287 T123 | T64 T287 T123 | T64 T287 T123 | T64 T287 T123 | T63 T64 T287 | T29 T63 T287 | T245 T287 T193 | T82 T83 T84 | T11 T12 T287 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T4 T13 T140 | T271 T82 T339 | T118 T146 T341 | T118 T146 T341 | T287 T123 T331 | T287 T344 T123 | T287 T123 T331 | T287 T123 T331 | T127 T128 T287 | T127 T128 T287 | T127 T128 T287 | T127 T128 T287 | T127 T128 T287 | T130 T131 T287 | T130 T131 T287 | T130 T131 T287 | T130 T131 T287 | T3 T130 T131 | T3 T287 T65 | T3 T287 T65 | T3 T287 T65 | T3 T287 T65 | T37 T287 T123 | T37 T287 T123 | T37 T287 T123 | T37 T287 T123 | T27 T37 T287 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T14 T11 | T14 T287 T123 | T14 T11 T12 | T14 T287 T123 | T5 T287 T123 | T5 T287 T123 | T5 T287 T123 | T5 T287 T123 | T5 T287 T123 | T5 T287 T123 | T287 T123 T331 | T287 T123 T331 | T61 T287 T123 | T61 T287 T123 | T61 T287 T123 | T61 T287 T123 | T61 T287 T123 | T287 T123 T331 | T287 T123 T331 | T64 T287 T123 | T64 T287 T123 | T64 T287 T123 | T64 T287 T123 | T64 T287 T123 | T63 T64 T287 | T63 T287 T123 | T63 T287 T123 | T29 T287 T123 | T287 T123 T331 | T82 T83 T84 | T82 T83 T84 | T11 T82 T12 | T11 T12 T287 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T4 T13 T339 | T140 T68 T287 | T271 T82 T339 | T178 T287 T123 | T118 T146 T341 | T118 T146 T341 | T118 T146 T341 | T294 T342 T287 | T287 T123 T331 | T287 T123 T331 | T287 T344 T123 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331
86 (vld_tree[C0] & vld_tree[C1] & logic'(max_tree[C1] > max_tree[C0]));
87 // Forwarding muxes
88 // Note: these ternaries have triggered a synthesis bug in Vivado versions older
89 // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
90 188/188(67 unreachable) assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
Tests: T3 T4 T5 | T3 T5 T29 | T4 T118 T13 | T3 T27 T130 | T5 T29 T27 | T4 T118 T13 | T3 T130 T127 | T27 T37 T331 | T5 T27 T14 | T29 T63 T61 | T4 T13 T271 | T118 T146 T341 | T130 T127 T131 | T3 T130 T131 | T27 T37 T331 | T27 T334 T42 | T5 T27 T14 | T5 T61 T334 | T61 T64 T334 | T29 T63 T64 | T82 T83 T84 | T4 T13 T271 | T118 T146 T341 | T334 T345 T346 | T127 T128 T331 | T130 T127 T131 | T3 T130 T131 | T3 T37 T65 | T27 T37 T331 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T11 T123 | T5 T14 T123 | T5 T334 T60 | T61 T334 T62 | T61 T334 T62 | T64 T334 T139 | T63 T64 T334 | T29 T245 T193 | T82 T83 T84 | T331 T332 T333 | T331 T332 T333 | T4 T13 T271 | T118 T146 T341 | T344 T123 T334 | T334 T345 T346 | T334 T345 T346 | T127 T128 T331 | T127 T128 T331 | T130 T127 T131 | T130 T131 T331 | T3 T130 T131 | T3 T65 T331 | T3 T65 T331 | T37 T331 T66 | T331 T332 T333 | T27 T37 T331 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T11 T123 | T14 T123 T50 | T5 T123 T334 | T334 T335 T336 | T5 T334 T60 | T334 T335 T336 | T61 T334 T62 | T334 T335 T336 | T61 T334 T62 | T64 T334 T139 | T64 T334 T139 | T334 T335 T336 | T63 T64 T334 | T29 T123 T334 | T245 T193 T123 | T82 T83 T84 | T123 T331 T191 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T4 T13 T140 | T271 T339 T272 | T118 T146 T341 | T118 T146 T341 | T123 T334 T191 | T344 T123 T334 | T334 T335 T336 | T334 T345 T346 | T334 T345 T346 | T127 T128 T331 | T127 T128 T331 | T127 T128 T331 | T331 T332 T333 | T127 T128 T331 | T130 T131 T331 | T130 T131 T331 | T331 T332 T333 | T331 T332 T333 | T3 T130 T131 | T3 T65 T331 | T3 T65 T331 | T331 T332 T333 | T3 T65 T331 | T37 T331 T66 | T37 T331 T66 | T331 T332 T333 | T331 T332 T333 | T27 T37 T331 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T11 T123 | T123 T191 T192 | T123 T191 T192 | T14 T123 T50 | T5 T123 T334 | T5 T334 T60 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T5 T334 T60 | T334 T335 T336 | T334 T335 T336 | T61 T334 T62 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T61 T334 T62 | T334 T335 T336 | T334 T335 T336 | T64 T334 T139 | T64 T334 T139 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T63 T64 T334 | T334 T335 T336 | T334 T335 T336 | T29 T123 T135 | T123 T191 T192 | T245 T193 T123 | T84 T293 T280 | T82 T83 T193 | T123 T191 T192 | T123 T331 T191 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T4 T13 T292 | T140 T68 T331 | T271 T339 T272 | T178 T123 T340 | T118 T146 T341 | T146 T341 T334 | T118 T146 T341 | T294 T342 T343 | T123 T334 T191 | T123 T191 T192 | T344 T123 T182 | T334 T345 T346 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T345 T346 | T334 T345 T346
91 188/255 ==> assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
Tests: T3 T4 T5 | T3 T5 T29 | T4 T118 T13 | T3 T27 T130 | T5 T29 T27 | T4 T118 T13 | T3 T130 T127 | T27 T37 T331 | T5 T27 T14 | T29 T63 T61 | T4 T13 T271 | T118 T146 T341 | T130 T127 T131 | T3 T130 T131 | T27 T37 T331 | T27 T334 T42 | T5 T27 T14 | T5 T61 T334 | T61 T64 T334 | T29 T63 T64 | T82 T83 T193 | T4 T13 T271 | T118 T146 T341 | T334 T345 T346 | T127 T128 T331 | T130 T127 T131 | T3 T130 T131 | T3 T37 T65 | T27 T37 T331 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T11 T123 | T5 T14 T123 | T5 T334 T60 | T61 T334 T62 | T61 T334 T62 | T64 T334 T139 | T63 T64 T334 | T29 T245 T193 | T82 T83 T193 | T331 T332 T333 | T331 T332 T333 | T4 T13 T271 | T118 T146 T341 | T344 T123 T334 | T334 T345 T346 | T334 T335 T336 | T127 T128 T331 | T331 T332 T333 | T130 T127 T131 | T130 T131 T331 | T3 T130 T131 | T3 T65 T331 | T3 T65 T331 | T37 T331 T66 | T331 T332 T333 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T11 T123 T229 | T14 T123 T50 | T5 T334 T60 | T334 T335 T336 | T5 T334 T60 | T334 T335 T336 | T61 T334 T62 | T334 T335 T336 | T61 T334 T62 | T64 T334 T139 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T29 T123 T334 | T245 T193 T123 | T82 T83 T193 | T123 T331 T191 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T4 T13 T140 | T271 T272 T178 | T118 T146 T341 | T294 T342 T343 | T123 T191 T192 | T123 T334 T345 | T334 T335 T336 | T334 T345 T346 | T334 T335 T336 | T127 T128 T331 | T127 T128 T331 | T331 T332 T333 | T331 T332 T333 | T127 T128 T331 | T130 T131 T331 | T130 T131 T331 | T331 T332 T333 | T331 T332 T333 | T3 T65 T331 | T3 T65 T331 | T331 T332 T333 | T331 T332 T333 | T3 T65 T331 | T37 T331 T66 | T37 T331 T66 | T331 T332 T333 | T331 T332 T333 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T27 T334 T42 | T11 T123 T229 | T123 T191 T192 | T123 T191 T192 | T123 T191 T192 | T5 T334 T60 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T61 T334 T62 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T61 T334 T62 | T334 T335 T336 | T334 T335 T336 | T64 T334 T139 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T29 T123 T191 | T123 T191 T192 | T245 T193 T337 | T338 T334 T277 | T123 T191 T192 | T123 T191 T192 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T4 T13 T292 | T140 T334 T141 | T271 T272 T193 | T123 T191 T192 | T118 T146 T341 | T146 T341 T334 | T334 T335 T336 | T334 T335 T336 | T123 T191 T192 | T123 T191 T192 | T123 T191 T192 | T334 T345 T346 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336 | T334 T335 T336
92 188/255 ==> assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
Tests: T3 T4 T5 | T3 T5 T29 | T4 T118 T13 | T3 T27 T130 | T5 T29 T27 | T4 T118 T13 | T3 T130 T127 | T27 T37 T287 | T5 T27 T14 | T29 T63 T61 | T4 T13 T271 | T118 T146 T341 | T130 T127 T131 | T3 T130 T131 | T27 T37 T287 | T27 T287 T123 | T5 T27 T14 | T5 T61 T287 | T61 T64 T287 | T29 T63 T64 | T82 T83 T84 | T4 T13 T271 | T118 T146 T341 | T287 T123 T331 | T127 T128 T287 | T130 T127 T131 | T3 T130 T131 | T3 T37 T287 | T27 T37 T287 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T11 T287 | T5 T14 T11 | T5 T287 T123 | T61 T287 T123 | T61 T287 T123 | T64 T287 T123 | T63 T64 T287 | T29 T63 T245 | T11 T82 T12 | T287 T123 T331 | T287 T123 T331 | T4 T13 T271 | T118 T146 T341 | T287 T344 T123 | T287 T123 T331 | T287 T123 T331 | T127 T128 T287 | T127 T128 T287 | T130 T127 T131 | T130 T131 T287 | T3 T130 T131 | T3 T287 T65 | T3 T287 T65 | T37 T287 T123 | T37 T287 T123 | T27 T37 T287 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T14 T11 | T14 T11 T12 | T5 T287 T123 | T5 T287 T123 | T5 T287 T123 | T287 T123 T331 | T61 T287 T123 | T61 T287 T123 | T61 T287 T123 | T64 T287 T123 | T64 T287 T123 | T64 T287 T123 | T63 T64 T287 | T29 T63 T287 | T245 T287 T193 | T82 T83 T84 | T11 T12 T287 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T4 T13 T140 | T271 T82 T339 | T118 T146 T341 | T118 T146 T341 | T287 T123 T331 | T287 T344 T123 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T127 T128 T287 | T127 T128 T287 | T127 T128 T287 | T127 T128 T287 | T127 T128 T287 | T130 T131 T287 | T130 T131 T287 | T130 T131 T287 | T130 T131 T287 | T3 T130 T131 | T3 T287 T65 | T3 T287 T65 | T3 T287 T65 | T3 T287 T65 | T37 T287 T123 | T37 T287 T123 | T37 T287 T123 | T37 T287 T123 | T27 T37 T287 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T287 T123 | T27 T14 T11 | T14 T287 T123 | T14 T11 T12 | T14 T287 T123 | T5 T287 T123 | T5 T287 T123 | T5 T287 T123 | T5 T287 T123 | T5 T287 T123 | T5 T287 T123 | T287 T123 T331 | T287 T123 T331 | T61 T287 T123 | T61 T287 T123 | T61 T287 T123 | T61 T287 T123 | T61 T287 T123 | T287 T123 T331 | T287 T123 T331 | T64 T287 T123 | T64 T287 T123 | T64 T287 T123 | T64 T287 T123 | T64 T287 T123 | T63 T64 T287 | T63 T287 T123 | T63 T287 T123 | T29 T287 T123 | T287 T123 T331 | T82 T83 T84 | T82 T83 T84 | T11 T82 T12 | T11 T12 T287 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T4 T13 T339 | T140 T68 T287 | T271 T82 T339 | T178 T287 T123 | T118 T146 T341 | T118 T146 T341 | T118 T146 T341 | T294 T342 T287 | T287 T123 T331 | T287 T123 T331 | T287 T344 T123 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331 | T287 T123 T331
93 end
94 end : gen_level
95 end : gen_tree
96
97
98 // The results can be found at the tree root
99 1/1 assign max_valid_o = vld_tree[0];
Tests: T3 T4 T5
100 1/1 assign max_idx_o = idx_tree[0];
Tests: T3 T4 T5
101 1/1 assign max_value_o = max_tree[0];
Tests: T3 T4 T5
102
103 ////////////////
104 // Assertions //
105 ////////////////
106
107 `ifdef INC_ASSERT
108 //VCS coverage off
109 // pragma coverage off
110
111 // Helper functions for assertions below.
112 function automatic logic [Width-1:0] max_value (input logic [NumSrc-1:0][Width-1:0] values_i,
113 input logic [NumSrc-1:0] valid_i);
114 unreachable logic [Width-1:0] value = '0;
115 unreachable for (int k = 0; k < NumSrc; k++) begin
116 unreachable if (valid_i[k] && values_i[k] > value) begin
117 unreachable value = values_i[k];
118 end
==> MISSING_ELSE
119 end
120 unreachable return value;
121 endfunction : max_value
122
123 function automatic logic [SrcWidth-1:0] max_idx (input logic [NumSrc-1:0][Width-1:0] values_i,
124 input logic [NumSrc-1:0] valid_i);
125 unreachable logic [Width-1:0] value = '0;
126 unreachable logic [SrcWidth-1:0] idx = '0;
127 unreachable for (int k = NumSrc-1; k >= 0; k--) begin
128 unreachable if (valid_i[k] && values_i[k] >= value) begin
129 unreachable value = values_i[k];
130 unreachable idx = k;
131 end
==> MISSING_ELSE
132 end
133 unreachable return idx;
134 endfunction : max_idx
135
136 logic [Width-1:0] max_value_exp;
137 logic [SrcWidth-1:0] max_idx_exp;
138 unreachable assign max_value_exp = max_value(values_i, valid_i);
139 unreachable assign max_idx_exp = max_idx(values_i, valid_i);