Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	138921	1			T95	8		T96	2		T97	4
values[2]	10963	1			T548	1		T457	5		T562	1
values[3]	4647	1			T457	9		T433	33		T644	59
values[4]	2685	1			T457	6		T433	33		T644	19
values[5]	1738	1			T457	9		T433	20		T644	12
values[6]	1200	1			T457	3		T433	17		T644	8
values[7]	840	1			T457	4		T433	7		T644	5
values[8]	605	1			T457	5		T433	4		T476	1
values[9]	493	1			T457	5		T433	2		T476	2
values[10]	492	1			T457	5		T433	4		T476	2
values[11]	425	1			T457	4		T433	2		T476	1
values[12]	391	1			T457	5		T476	6		T480	2
values[13]	375	1			T457	24		T476	6		T514	10
values[14]	306	1			T457	6		T476	1		T514	14
values[15]	315	1			T457	4		T476	2		T514	5
values[16]	293	1			T457	11		T514	4		T607	1
values[17]	285	1			T457	11		T514	6		T607	4
values[18]	290	1			T457	3		T514	11		T607	7
values[19]	264	1			T457	7		T514	4		T607	1
values[20]	287	1			T457	2		T514	9		T607	1
values[21]	311	1			T457	7		T514	5		T607	2
values[22]	346	1			T457	8		T514	21		T607	1
values[23]	301	1			T457	18		T514	4		T607	2
values[24]	313	1			T457	11		T514	4		T607	4
values[25]	291	1			T457	4		T514	8		T607	8
values[26]	332	1			T457	5		T514	3		T607	7
values[27]	302	1			T457	6		T514	6		T607	6
values[28]	310	1			T457	7		T514	8		T607	6
values[29]	290	1			T457	14		T514	7		T607	4
values[30]	317	1			T457	9		T514	14		T607	2
values[31]	270	1			T457	4		T514	7		T607	1
values[32]	327	1			T457	9		T514	7		T607	1
values[33]	325	1			T457	4		T514	4		T607	1
values[34]	278	1			T457	3		T514	2		T607	6
values[35]	341	1			T457	7		T514	8		T607	10
values[36]	315	1			T457	6		T514	4		T607	2
values[37]	293	1			T457	7		T514	8		T607	2
values[38]	312	1			T457	6		T514	19		T607	1
values[39]	292	1			T457	11		T514	7		T607	2
values[40]	270	1			T457	9		T514	9		T607	2
values[41]	282	1			T457	8		T514	6		T607	3
values[42]	307	1			T457	6		T514	4		T607	2
values[43]	279	1			T457	7		T514	5		T607	1
values[44]	320	1			T457	13		T514	5		T607	1
values[45]	321	1			T457	10		T514	8		T607	2
values[46]	290	1			T457	10		T514	4		T607	1
values[47]	279	1			T457	5		T514	2		T607	2
values[48]	259	1			T457	4		T514	11		T607	2
values[49]	262	1			T457	6		T514	3		T607	3
values[50]	237	1			T457	5		T514	9		T607	3
values[51]	221	1			T457	6		T514	4		T607	1
values[52]	264	1			T457	8		T514	5		T607	2
values[53]	262	1			T457	18		T514	6		T607	2
values[54]	250	1			T457	16		T514	3		T607	2
values[55]	230	1			T457	3		T514	8		T607	5
values[56]	226	1			T514	11		T607	10		T622	4
values[57]	243	1			T514	5		T607	6		T622	8
values[58]	223	1			T514	6		T607	1		T622	6
values[59]	220	1			T514	6		T607	2		T622	6
values[60]	228	1			T514	14		T607	4		T622	10
values[61]	198	1			T514	7		T607	2		T622	7
values[62]	210	1			T514	15		T607	1		T622	6
values[63]	172	1			T514	3		T607	2		T622	3
values[64]	219	1			T514	14		T607	1		T622	5
values[65]	186	1			T514	4		T607	4		T622	5
values[66]	179	1			T514	7		T607	5		T622	7
values[67]	192	1			T514	2		T607	4		T622	16
values[68]	182	1			T514	16		T607	7		T622	11
values[69]	163	1			T514	13		T607	1		T622	4
values[70]	141	1			T514	4		T607	1		T622	11
values[71]	185	1			T514	5		T607	4		T622	9
values[72]	184	1			T514	6		T607	10		T622	7
values[73]	149	1			T607	7		T622	9		T787	5
values[74]	138	1			T607	1		T622	3		T787	16
values[75]	111	1			T607	1		T622	11		T787	12
values[76]	107	1			T607	2		T622	14		T787	5
values[77]	94	1			T607	2		T622	9		T787	8
values[78]	75	1			T607	1		T622	6		T787	2
values[79]	57	1			T607	2		T622	2		T788	1
values[80]	73	1			T607	4		T622	2		T788	1
values[81]	83	1			T607	1		T622	5		T788	1
values[82]	81	1			T607	2		T622	3		T788	1
values[83]	67	1			T607	3		T622	5		T788	3
values[84]	80	1			T607	6		T622	2		T788	3
values[85]	89	1			T607	2		T622	4		T788	8
values[86]	83	1			T607	3		T622	7		T788	6
values[87]	94	1			T607	1		T622	5		T788	5
values[88]	101	1			T607	5		T622	6		T788	5
values[89]	93	1			T607	1		T622	4		T788	1
values[90]	90	1			T607	5		T622	7		T788	4
values[91]	85	1			T607	1		T622	3		T788	2
values[92]	90	1			T607	1		T622	6		T788	1
values[93]	86	1			T607	4		T622	6		T788	1
values[94]	87	1			T607	7		T622	14		T788	1
values[95]	102	1			T607	5		T622	12		T788	2
values[96]	95	1			T607	8		T622	10		T788	3
values[97]	91	1			T607	6		T622	9		T788	1
values[98]	82	1			T607	2		T622	7		T788	2
values[99]	81	1			T607	7		T622	6		T788	3
values[100]	71	1			T607	8		T622	7		T788	2
values[101]	78	1			T607	7		T622	5		T788	4
values[102]	80	1			T607	3		T622	6		T788	2
values[103]	85	1			T607	4		T622	4		T788	3
values[104]	97	1			T607	7		T622	3		T788	1
values[105]	70	1			T607	10		T788	2		T789	1
values[106]	91	1			T607	4		T788	4		T789	1
values[107]	87	1			T607	2		T788	3		T789	1
values[108]	83	1			T607	3		T788	2		T789	1
values[109]	102	1			T607	5		T788	5		T789	1
values[110]	86	1			T607	2		T788	4		T789	1
values[111]	70	1			T607	4		T788	1		T789	3
values[112]	71	1			T607	3		T788	1		T789	1
values[113]	65	1			T607	4		T788	1		T789	3
values[114]	74	1			T607	3		T788	1		T789	1
values[115]	94	1			T607	2		T788	2		T789	6
values[116]	82	1			T607	2		T788	4		T789	3
values[117]	81	1			T607	1		T788	1		T789	2
values[118]	88	1			T607	4		T788	1		T789	2
values[119]	91	1			T607	5		T788	1		T789	1
values[120]	79	1			T607	4		T788	2		T789	1
values[121]	74	1			T607	6		T788	3		T789	1
values[122]	81	1			T607	3		T788	1		T789	2
values[123]	86	1			T607	2		T788	3		T789	1
values[124]	95	1			T607	2		T788	4		T789	1
values[125]	104	1			T607	1		T788	5		T789	1
values[126]	198	1			T607	11		T788	3		T789	3
values[127]	1148	1			T607	5		T788	24		T789	41
values[128]	8253	1			T607	1		T788	259		T789	327

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	150506	1			T95	9		T96	3		T97	1
values[2]	4107	1			T559	1		T458	4		T550	8
values[3]	1947	1			T550	4		T482	1		T644	4
values[4]	1517	1			T550	2		T482	1		T644	4
values[5]	1198	1			T550	3		T482	2		T644	1
values[6]	1028	1			T550	1		T482	2		T644	2
values[7]	878	1			T550	5		T482	2		T644	5
values[8]	786	1			T550	3		T482	8		T644	2
values[9]	792	1			T550	4		T482	3		T644	1
values[10]	739	1			T550	7		T482	1		T644	1
values[11]	622	1			T550	15		T482	2		T644	4
values[12]	547	1			T550	18		T482	2		T644	2
values[13]	555	1			T550	10		T482	2		T644	4
values[14]	570	1			T550	13		T482	2		T644	4
values[15]	589	1			T550	16		T482	1		T644	1
values[16]	482	1			T550	23		T482	1		T644	3
values[17]	440	1			T550	26		T482	2		T644	1
values[18]	447	1			T550	27		T482	9		T644	2
values[19]	326	1			T550	18		T482	6		T644	7
values[20]	381	1			T550	14		T482	3		T644	4
values[21]	427	1			T550	16		T482	4		T644	4
values[22]	424	1			T550	20		T482	1		T644	2
values[23]	419	1			T550	13		T482	1		T644	1
values[24]	348	1			T550	7		T482	4		T644	3
values[25]	332	1			T550	3		T482	2		T644	2
values[26]	316	1			T550	5		T482	4		T644	5
values[27]	228	1			T550	5		T482	11		T644	2
values[28]	207	1			T550	8		T482	7		T644	2
values[29]	214	1			T550	17		T482	2		T644	1
values[30]	176	1			T550	9		T482	1		T644	2
values[31]	174	1			T550	5		T482	1		T644	1
values[32]	175	1			T550	4		T482	1		T644	4
values[33]	167	1			T550	8		T482	1		T644	3
values[34]	116	1			T550	4		T482	1		T644	1
values[35]	133	1			T550	9		T482	3		T644	3
values[36]	136	1			T550	6		T482	7		T644	6
values[37]	155	1			T550	1		T482	2		T644	5
values[38]	154	1			T550	3		T482	3		T644	1
values[39]	193	1			T550	4		T482	2		T644	1
values[40]	195	1			T550	2		T482	3		T644	2
values[41]	195	1			T550	15		T482	1		T644	1
values[42]	191	1			T550	24		T482	7		T644	3
values[43]	153	1			T550	19		T482	1		T644	5
values[44]	132	1			T550	18		T482	3		T644	5
values[45]	112	1			T550	5		T482	1		T644	3
values[46]	109	1			T550	19		T482	4		T644	3
values[47]	99	1			T550	10		T482	2		T644	3
values[48]	117	1			T550	21		T482	5		T644	2
values[49]	98	1			T550	17		T482	3		T644	1
values[50]	109	1			T550	23		T482	1		T644	3
values[51]	114	1			T550	17		T482	3		T644	6
values[52]	99	1			T550	8		T482	1		T644	4
values[53]	80	1			T482	1		T644	2		T477	2
values[54]	71	1			T482	3		T644	5		T477	6
values[55]	74	1			T482	1		T644	4		T477	9
values[56]	74	1			T482	3		T644	3		T477	7
values[57]	69	1			T482	3		T644	3		T477	8
values[58]	77	1			T482	3		T644	4		T477	3
values[59]	70	1			T482	6		T644	1		T477	3
values[60]	65	1			T482	3		T644	2		T477	3
values[61]	79	1			T482	3		T644	5		T477	2
values[62]	69	1			T482	3		T644	2		T477	5
values[63]	70	1			T482	2		T644	1		T477	6
values[64]	64	1			T482	2		T644	2		T477	7
values[65]	72	1			T482	2		T644	2		T477	5
values[66]	66	1			T482	2		T644	2		T477	3
values[67]	63	1			T482	4		T644	1		T477	3
values[68]	70	1			T482	5		T644	3		T477	6
values[69]	82	1			T482	10		T644	3		T477	6
values[70]	73	1			T482	4		T644	1		T477	8
values[71]	82	1			T482	5		T644	4		T477	6
values[72]	85	1			T482	4		T644	9		T477	4
values[73]	70	1			T482	1		T644	5		T477	6
values[74]	76	1			T482	1		T644	2		T477	4
values[75]	63	1			T482	2		T644	5		T477	4
values[76]	74	1			T482	5		T644	2		T477	12
values[77]	73	1			T482	1		T644	2		T477	8
values[78]	101	1			T482	1		T644	6		T477	10
values[79]	70	1			T482	3		T644	3		T477	6
values[80]	66	1			T482	2		T644	1		T477	6
values[81]	86	1			T482	1		T644	3		T477	8
values[82]	93	1			T482	3		T644	7		T477	8
values[83]	107	1			T482	2		T644	4		T477	6
values[84]	112	1			T482	2		T644	7		T477	12
values[85]	110	1			T482	4		T644	13		T477	3
values[86]	107	1			T482	2		T644	9		T477	6
values[87]	97	1			T482	3		T644	7		T477	3
values[88]	97	1			T482	2		T644	3		T477	5
values[89]	98	1			T482	1		T644	2		T477	4
values[90]	83	1			T482	2		T644	3		T477	4
values[91]	93	1			T482	1		T644	6		T477	7
values[92]	89	1			T482	2		T644	7		T477	3
values[93]	96	1			T482	3		T644	1		T477	13
values[94]	97	1			T482	6		T644	2		T477	8
values[95]	102	1			T482	1		T644	3		T477	3
values[96]	102	1			T482	1		T644	4		T477	2
values[97]	97	1			T482	1		T644	2		T477	2
values[98]	116	1			T482	2		T644	2		T477	5
values[99]	109	1			T482	3		T644	2		T477	8
values[100]	118	1			T482	2		T644	9		T477	9
values[101]	99	1			T482	2		T644	4		T477	11
values[102]	104	1			T482	2		T644	6		T477	6
values[103]	107	1			T482	1		T644	5		T477	11
values[104]	96	1			T482	4		T644	3		T477	2
values[105]	97	1			T482	2		T644	3		T477	5
values[106]	118	1			T482	6		T644	1		T477	4
values[107]	112	1			T482	6		T644	4		T477	9
values[108]	116	1			T482	3		T644	9		T477	10
values[109]	117	1			T482	5		T644	8		T477	10
values[110]	111	1			T482	2		T644	6		T477	11
values[111]	128	1			T482	9		T644	7		T477	15
values[112]	97	1			T482	4		T644	4		T477	8
values[113]	108	1			T482	5		T644	2		T477	8
values[114]	145	1			T482	4		T644	5		T477	10
values[115]	123	1			T482	7		T644	3		T477	11
values[116]	113	1			T482	6		T644	2		T477	7
values[117]	120	1			T482	4		T644	1		T477	6
values[118]	141	1			T482	4		T644	4		T477	5
values[119]	139	1			T482	1		T644	11		T477	6
values[120]	119	1			T482	5		T644	12		T477	3
values[121]	124	1			T482	3		T644	5		T477	3
values[122]	111	1			T482	2		T644	3		T477	4
values[123]	167	1			T482	8		T644	4		T477	17
values[124]	251	1			T482	7		T644	23		T477	35
values[125]	406	1			T482	16		T644	24		T477	57
values[126]	881	1			T482	9		T644	10		T477	74
values[127]	3333	1			T482	7		T644	7		T477	52
values[128]	5749	1			T482	1		T477	2		T472	2

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	135032	1			T95	8		T96	2		T97	2
values[2]	9842	1			T163	1		T188	2		T478	1
values[3]	4010	1			T564	1		T550	110		T686	118
values[4]	2364	1			T550	55		T686	70		T560	6
values[5]	1436	1			T550	27		T686	40		T560	7
values[6]	996	1			T550	4		T686	3		T560	6
values[7]	694	1			T560	12		T474	6		T790	5
values[8]	504	1			T560	5		T474	3		T790	2
values[9]	437	1			T474	11		T790	10		T472	9
values[10]	344	1			T474	4		T790	12		T472	13
values[11]	295	1			T474	4		T790	8		T472	4
values[12]	277	1			T474	5		T790	4		T514	5
values[13]	228	1			T474	10		T790	6		T514	2
values[14]	236	1			T474	3		T790	6		T514	5
values[15]	209	1			T474	8		T790	3		T514	21
values[16]	171	1			T474	7		T790	3		T514	9
values[17]	179	1			T474	3		T790	8		T514	7
values[18]	192	1			T474	12		T790	17		T514	8
values[19]	166	1			T474	10		T790	5		T514	4
values[20]	153	1			T474	7		T790	5		T514	3
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