Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.21 95.55 94.16 95.35 95.08 97.53 99.61


Total tests in report: 2935
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
39.58 39.58 46.17 46.17 44.60 44.60 24.61 24.61 59.35 59.35 62.59 62.59 0.13 0.13 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.438640143
47.28 7.70 50.85 4.67 55.31 10.71 24.87 0.26 68.17 8.82 83.57 20.98 0.90 0.78 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.107226107
52.46 5.18 62.01 11.16 62.67 7.36 27.31 2.44 78.29 10.12 83.57 0.00 0.90 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.917889090
56.76 4.30 72.10 10.10 63.90 1.23 33.91 6.61 78.62 0.33 83.57 0.00 8.42 7.52 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3786136531
60.87 4.11 72.10 0.00 63.95 0.05 33.91 0.00 78.62 0.00 83.57 0.00 33.06 24.64 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.4029830261
64.07 3.20 77.31 5.21 67.95 4.00 37.54 3.63 80.41 1.79 88.11 4.55 33.06 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3177563228
67.11 3.05 77.31 0.00 67.97 0.01 55.35 17.81 80.42 0.01 88.46 0.35 33.17 0.11 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1187677313
69.62 2.50 77.31 0.00 67.97 0.01 55.35 0.00 80.42 0.00 88.46 0.00 48.18 15.02 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.3896095772
71.93 2.32 78.77 1.46 70.51 2.54 60.67 5.32 82.08 1.66 88.81 0.35 50.76 2.57 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.555446173
74.07 2.14 82.06 3.28 74.52 4.02 62.24 1.57 85.67 3.59 89.16 0.35 50.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.4127744731
75.99 1.92 82.06 0.00 74.52 0.00 62.24 0.00 85.67 0.00 89.16 0.00 62.27 11.51 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.931137338
77.57 1.58 82.13 0.07 76.73 2.20 62.24 0.00 85.70 0.02 89.16 0.00 69.44 7.17 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.3442421851
79.04 1.48 84.53 2.40 78.92 2.20 63.89 1.65 88.30 2.60 89.16 0.00 69.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.406020193
80.46 1.41 84.67 0.14 79.02 0.10 71.79 7.90 88.48 0.18 89.34 0.17 69.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.3186747798
81.62 1.17 84.67 0.00 79.02 0.00 71.79 0.00 88.48 0.00 89.34 0.00 76.43 6.99 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.670732276
82.78 1.16 86.97 2.30 80.11 1.09 73.88 2.09 89.24 0.76 90.03 0.70 76.43 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.2231560800
83.73 0.96 87.85 0.88 80.83 0.72 77.14 3.26 90.11 0.87 90.03 0.00 76.44 0.01 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.2888985651
84.68 0.95 89.21 1.36 81.65 0.82 79.20 2.05 91.22 1.11 90.38 0.35 76.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.2544223703
85.57 0.89 89.21 0.00 81.65 0.00 79.20 0.00 91.22 0.00 90.38 0.00 81.78 5.33 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3357859021
86.45 0.88 89.96 0.75 81.98 0.33 79.21 0.01 91.53 0.31 94.23 3.85 81.78 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.955000592
87.29 0.84 89.96 0.00 81.98 0.00 84.24 5.03 91.53 0.00 94.23 0.00 81.78 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.3686380417
88.00 0.71 89.96 0.00 82.44 0.46 84.24 0.00 91.55 0.02 94.23 0.00 85.55 3.77 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.1460737829
88.65 0.66 90.50 0.54 82.99 0.54 84.44 0.20 92.11 0.56 96.33 2.10 85.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.677637967
89.26 0.61 91.17 0.67 85.24 2.25 84.86 0.42 92.43 0.32 96.33 0.00 85.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.1609158662
89.74 0.48 91.24 0.07 85.37 0.13 84.87 0.01 92.45 0.02 96.33 0.00 88.20 2.66 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.4026469050
90.22 0.47 91.35 0.11 85.41 0.05 87.53 2.66 92.47 0.02 96.33 0.00 88.20 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.4291001180
90.60 0.38 92.29 0.94 85.65 0.24 88.48 0.95 92.64 0.17 96.33 0.00 88.20 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.3614451398
90.98 0.38 92.34 0.04 87.48 1.82 88.48 0.00 92.65 0.01 96.33 0.00 88.61 0.41 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.4256600642
91.35 0.36 92.44 0.10 88.60 1.12 88.62 0.14 93.44 0.80 96.33 0.00 88.65 0.04 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.3432428634
91.71 0.36 92.44 0.00 88.61 0.01 88.62 0.00 93.44 0.00 96.33 0.00 90.81 2.16 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.1057537221
92.05 0.34 92.44 0.00 88.61 0.00 88.62 0.00 93.44 0.00 96.33 0.00 92.84 2.03 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1942022894
92.38 0.33 93.13 0.69 88.90 0.29 89.27 0.65 93.61 0.17 96.50 0.17 92.84 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1148605060
92.66 0.28 93.13 0.00 88.90 0.00 89.27 0.00 93.61 0.00 96.50 0.00 94.52 1.68 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.477827703
92.90 0.24 93.13 0.00 88.90 0.00 89.27 0.00 93.61 0.00 96.50 0.00 95.97 1.45 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.3432382513
93.12 0.22 93.51 0.38 89.32 0.42 89.33 0.06 94.05 0.44 96.50 0.00 95.97 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.1205417435
93.33 0.22 93.54 0.03 89.40 0.07 89.33 0.00 94.06 0.01 96.50 0.00 97.14 1.17 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.2476452915
93.54 0.21 93.54 0.00 89.40 0.00 90.57 1.24 94.06 0.00 96.50 0.00 97.14 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.176086425
93.72 0.19 93.54 0.00 90.51 1.12 90.57 0.00 94.06 0.00 96.50 0.00 97.14 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.52485170
93.88 0.15 93.54 0.00 90.51 0.00 91.49 0.92 94.06 0.00 96.50 0.00 97.14 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.325899041
94.00 0.13 93.78 0.23 90.84 0.32 91.70 0.22 94.06 0.00 96.50 0.00 97.14 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.639068465
94.12 0.12 93.79 0.01 90.85 0.02 92.37 0.67 94.06 0.00 96.50 0.00 97.14 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.4182429493
94.22 0.10 93.91 0.12 90.92 0.07 92.77 0.40 94.09 0.02 96.50 0.00 97.14 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.1417694282
94.32 0.09 93.91 0.01 91.02 0.10 92.77 0.01 94.10 0.02 96.50 0.00 97.59 0.45 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.1903900534
94.41 0.09 94.25 0.34 91.13 0.11 92.85 0.07 94.13 0.03 96.50 0.00 97.59 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.983727170
94.50 0.09 94.39 0.14 91.25 0.11 93.01 0.16 94.26 0.12 96.50 0.00 97.59 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2378426791
94.59 0.09 94.41 0.02 91.47 0.23 93.02 0.01 94.52 0.26 96.50 0.00 97.59 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1311621734
94.66 0.08 94.41 0.00 91.93 0.46 93.02 0.00 94.52 0.00 96.50 0.00 97.59 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.4279660198
94.74 0.07 94.41 0.00 91.93 0.00 93.47 0.44 94.52 0.00 96.50 0.00 97.59 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3937411980
94.79 0.06 94.41 0.00 91.98 0.05 93.47 0.00 94.53 0.02 96.50 0.00 97.87 0.28 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.4210451640
94.85 0.06 94.50 0.09 92.23 0.24 93.47 0.01 94.53 0.00 96.50 0.00 97.87 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.220401124
94.91 0.05 94.53 0.03 92.25 0.02 93.55 0.08 94.56 0.02 96.68 0.17 97.87 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.3691684376
94.96 0.05 94.56 0.03 92.27 0.02 93.78 0.23 94.57 0.02 96.68 0.00 97.87 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2458498824
95.00 0.05 94.56 0.00 92.31 0.04 93.78 0.00 94.59 0.02 96.68 0.00 98.10 0.22 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3791456401
95.05 0.05 94.56 0.00 92.44 0.13 93.78 0.00 94.73 0.15 96.68 0.00 98.10 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2241947700
95.09 0.04 94.57 0.01 92.45 0.01 93.78 0.00 94.76 0.02 96.85 0.17 98.11 0.01 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.2445071752
95.13 0.04 94.57 0.00 92.48 0.03 93.98 0.20 94.76 0.00 96.85 0.00 98.11 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.3757022342
95.16 0.04 94.64 0.07 92.48 0.00 94.13 0.15 94.77 0.01 96.85 0.00 98.11 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.3811113912
95.20 0.04 94.64 0.00 92.69 0.21 94.13 0.00 94.77 0.00 96.85 0.00 98.12 0.01 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.2813018504
95.24 0.04 94.65 0.01 92.70 0.01 94.13 0.01 94.77 0.01 97.03 0.17 98.13 0.01 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.1756272671
95.27 0.04 94.66 0.01 92.71 0.01 94.13 0.00 94.78 0.01 97.20 0.17 98.14 0.01 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.342093976
95.31 0.04 94.66 0.00 92.72 0.01 94.16 0.03 94.78 0.00 97.38 0.17 98.14 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1073434923
95.34 0.04 94.66 0.01 92.73 0.01 94.17 0.01 94.79 0.01 97.55 0.17 98.16 0.01 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3872413107
95.37 0.03 94.72 0.07 92.78 0.05 94.19 0.03 94.82 0.03 97.55 0.00 98.16 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.3114514287
95.40 0.03 94.74 0.01 92.79 0.01 94.33 0.14 94.82 0.00 97.55 0.00 98.16 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1307794740
95.42 0.03 94.74 0.00 92.79 0.00 94.49 0.15 94.82 0.00 97.55 0.00 98.16 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.2586513475
95.45 0.02 94.80 0.07 92.84 0.05 94.49 0.00 94.86 0.03 97.55 0.00 98.16 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.948145209
95.47 0.02 94.87 0.07 92.87 0.03 94.49 0.01 94.90 0.05 97.55 0.00 98.16 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.4098523969
95.50 0.02 94.87 0.00 92.95 0.08 94.49 0.00 94.94 0.03 97.55 0.00 98.19 0.04 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.1150513809
95.52 0.02 94.87 0.00 92.97 0.02 94.49 0.00 94.94 0.00 97.55 0.00 98.31 0.12 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.3273254037
95.54 0.02 94.88 0.01 93.01 0.04 94.55 0.05 94.97 0.03 97.55 0.00 98.31 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3996593350
95.56 0.02 94.88 0.00 93.05 0.04 94.55 0.00 94.99 0.02 97.55 0.00 98.38 0.07 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.408308953
95.58 0.02 94.88 0.00 93.17 0.12 94.55 0.00 94.99 0.00 97.55 0.00 98.38 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.3137363240
95.60 0.02 94.88 0.01 93.18 0.01 94.62 0.08 94.99 0.00 97.55 0.00 98.38 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3498725977
95.61 0.01 94.88 0.01 93.20 0.02 94.69 0.07 94.99 0.00 97.55 0.00 98.38 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2912150638
95.63 0.01 94.88 0.00 93.20 0.00 94.78 0.08 94.99 0.00 97.55 0.00 98.38 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.3206414978
95.64 0.01 94.89 0.01 93.25 0.05 94.78 0.00 95.00 0.02 97.55 0.00 98.38 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.28945536
95.66 0.01 94.91 0.01 93.29 0.04 94.79 0.01 95.02 0.02 97.55 0.00 98.38 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.1829501162
95.67 0.01 94.91 0.00 93.31 0.03 94.79 0.00 95.02 0.00 97.55 0.00 98.43 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.2773191504
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96.12 0.01 94.97 0.00 94.16 0.01 95.34 0.00 95.08 0.00 97.55 0.00 99.61 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2236353821
96.12 0.01 94.97 0.00 94.16 0.01 95.34 0.00 95.08 0.00 97.55 0.00 99.61 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.4265238660
96.12 0.01 94.97 0.00 94.16 0.00 95.34 0.01 95.08 0.00 97.55 0.00 99.61 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.3315764942
96.12 0.01 94.97 0.00 94.16 0.00 95.35 0.01 95.08 0.00 97.55 0.00 99.61 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2785045006
96.12 0.01 94.97 0.00 94.16 0.00 95.35 0.01 95.08 0.00 97.55 0.00 99.61 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1917294482
96.12 0.01 94.97 0.00 94.16 0.00 95.35 0.01 95.08 0.00 97.55 0.00 99.61 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.150684977

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.2366101760
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.3514795657
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3103753933
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.2047870877
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1054460870
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.352407784
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.3809140087
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2607886495
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.2369646960
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.3525576107
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.1964106195
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.4016204886
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.3605929757
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.3760590675
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.1255167786
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3273111747
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.1689688769
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.1671497023
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.2634006721
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1845174938
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.4093927278
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1486154005
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.291521971
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3852860136
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.742381550
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.419179621
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.2387581322
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.1938538868
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.2999643474
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.2834297892
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.1101540656
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.878508089
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1202705101
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.464561713
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.1462291614
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.472282366
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.1544816138
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.1218276788
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.3624140726
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.458851271
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.38633725
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.642943534
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.1036592197
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.2959096173
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.4225486787
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.275277077
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.1505601370
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.1477439122
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.2901058900
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1972931337
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.775387867
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.1178686574
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.4214365141
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.4080105842
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2428237309
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.2674326532
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.912865349
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.1166515118
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.4188037822
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.4252350750
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3724484150
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2134552582
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.3514608806
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.1277688557
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.3786286328
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.4117425479
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.2467193431
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.1802159889
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.743014719
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.629445906
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2911466041
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1387556797
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.3422987734
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.3209905157
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1855878548
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.1954966019
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.455760293
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.1723809033
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.3386661835
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.1076385054
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3245200162
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.1314463121
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.1700005033
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.3307491632
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.3468896891
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.3537803281
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.1968557967
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.2245913325
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.837004886
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1346120259
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.1089740246
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.1695348832
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2538569695
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.2377869415
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.2976158533
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.960572961
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.1480358946
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.1608296418
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.4183001818
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.16850111
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.3242357612
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.3107442387
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.2400294098
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.1857611485
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.3374191702
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.828855821
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.3253142127
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.2077108952
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.743644553
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2691384927
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.592503831
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3477656995
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.1227911176
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.647871126
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.4139023938
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.1566419214
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.2454080156
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.600250279
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.1374918931
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.26783745
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.1067841482
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.795885090
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Total test records in report: 2935
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TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.2828062985 Aug 27 10:33:21 PM UTC 24 Aug 27 10:35:16 PM UTC 24 2427463024 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.526085488 Aug 27 10:34:41 PM UTC 24 Aug 27 10:37:31 PM UTC 24 2856589244 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.1524254193 Aug 27 10:35:10 PM UTC 24 Aug 27 10:37:50 PM UTC 24 3004671936 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.3114514287 Aug 27 10:34:50 PM UTC 24 Aug 27 10:38:24 PM UTC 24 3539044700 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.326886244 Aug 27 10:37:02 PM UTC 24 Aug 27 10:39:30 PM UTC 24 2878523370 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2458498824 Aug 27 10:38:10 PM UTC 24 Aug 27 10:42:40 PM UTC 24 3753450146 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.712446257 Aug 27 10:39:40 PM UTC 24 Aug 27 10:42:47 PM UTC 24 3551777200 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3620276432 Aug 27 10:40:03 PM UTC 24 Aug 27 10:42:48 PM UTC 24 2217546471 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.438640143 Aug 27 10:39:15 PM UTC 24 Aug 27 10:43:11 PM UTC 24 3548943000 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_entropy.2202396665 Aug 27 10:39:32 PM UTC 24 Aug 27 10:43:21 PM UTC 24 3191298968 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.4038924347 Aug 27 10:39:32 PM UTC 24 Aug 27 10:43:53 PM UTC 24 3410159360 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.4127744731 Aug 27 10:39:10 PM UTC 24 Aug 27 10:44:29 PM UTC 24 2431690832 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2576572611 Aug 27 10:39:57 PM UTC 24 Aug 27 10:44:38 PM UTC 24 3021487080 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_vbus.248333504 Aug 27 10:39:41 PM UTC 24 Aug 27 10:44:45 PM UTC 24 2742906492 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.3976514810 Aug 27 10:40:01 PM UTC 24 Aug 27 10:45:20 PM UTC 24 2967930712 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.1056496941 Aug 27 10:39:11 PM UTC 24 Aug 27 10:45:31 PM UTC 24 3761462834 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.1417694282 Aug 27 10:39:20 PM UTC 24 Aug 27 10:45:31 PM UTC 24 2745075232 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.3614451398 Aug 27 10:38:19 PM UTC 24 Aug 27 10:45:40 PM UTC 24 4669460208 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3996593350 Aug 27 10:39:44 PM UTC 24 Aug 27 10:45:54 PM UTC 24 3929991272 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.4233470398 Aug 27 10:44:19 PM UTC 24 Aug 27 10:46:56 PM UTC 24 3860719168 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.64365728 Aug 27 10:37:19 PM UTC 24 Aug 27 10:47:00 PM UTC 24 3747118340 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.854125220 Aug 27 10:45:24 PM UTC 24 Aug 27 10:47:03 PM UTC 24 1850074170 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.244552814 Aug 27 10:42:46 PM UTC 24 Aug 27 10:47:06 PM UTC 24 3254154252 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2372396634 Aug 27 10:45:21 PM UTC 24 Aug 27 10:47:32 PM UTC 24 2361322111 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.1667056560 Aug 27 10:37:59 PM UTC 24 Aug 27 10:47:32 PM UTC 24 4770311032 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.4221642149 Aug 27 10:39:30 PM UTC 24 Aug 27 10:47:34 PM UTC 24 4611529388 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3124869530 Aug 27 10:44:17 PM UTC 24 Aug 27 10:47:38 PM UTC 24 3777569690 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.1816478591 Aug 27 10:38:55 PM UTC 24 Aug 27 10:47:44 PM UTC 24 4227310460 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.356280806 Aug 27 10:37:21 PM UTC 24 Aug 27 10:47:52 PM UTC 24 6062603700 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3498725977 Aug 27 10:39:57 PM UTC 24 Aug 27 10:47:53 PM UTC 24 4483765284 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.3924626493 Aug 27 10:38:27 PM UTC 24 Aug 27 10:47:55 PM UTC 24 4039747206 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.1829501162 Aug 27 10:38:48 PM UTC 24 Aug 27 10:48:10 PM UTC 24 4269190174 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.325899041 Aug 27 10:44:09 PM UTC 24 Aug 27 10:48:33 PM UTC 24 4066393953 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1187677313 Aug 27 10:39:31 PM UTC 24 Aug 27 10:48:49 PM UTC 24 4559227775 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.2544223703 Aug 27 10:38:46 PM UTC 24 Aug 27 10:48:50 PM UTC 24 5530391712 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.1581299707 Aug 27 10:39:36 PM UTC 24 Aug 27 10:49:12 PM UTC 24 4259822746 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2979898227 Aug 27 10:39:25 PM UTC 24 Aug 27 10:49:13 PM UTC 24 4434614392 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.2514813883 Aug 27 10:39:58 PM UTC 24 Aug 27 10:49:48 PM UTC 24 5498718560 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.593051362 Aug 27 10:39:23 PM UTC 24 Aug 27 10:49:48 PM UTC 24 3869488789 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.2351987189 Aug 27 10:39:46 PM UTC 24 Aug 27 10:49:55 PM UTC 24 4007928562 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.4182429493 Aug 27 10:40:21 PM UTC 24 Aug 27 10:50:01 PM UTC 24 5306868726 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.2040391416 Aug 27 10:38:54 PM UTC 24 Aug 27 10:50:06 PM UTC 24 5127421248 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.809234425 Aug 27 10:43:56 PM UTC 24 Aug 27 10:50:07 PM UTC 24 5171411056 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1782340394 Aug 27 10:39:21 PM UTC 24 Aug 27 10:50:12 PM UTC 24 4301515906 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.2164666289 Aug 27 10:39:34 PM UTC 24 Aug 27 10:50:29 PM UTC 24 5861365624 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.730866393 Aug 27 10:38:38 PM UTC 24 Aug 27 10:50:33 PM UTC 24 5226112288 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.2423344722 Aug 27 10:46:44 PM UTC 24 Aug 27 10:51:07 PM UTC 24 2905316216 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2313813590 Aug 27 10:39:34 PM UTC 24 Aug 27 10:51:43 PM UTC 24 4676121904 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.1093705065 Aug 27 10:46:36 PM UTC 24 Aug 27 10:52:05 PM UTC 24 4441216970 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3207139385 Aug 27 10:38:12 PM UTC 24 Aug 27 10:52:42 PM UTC 24 5825345537 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.205890609 Aug 27 10:35:16 PM UTC 24 Aug 27 10:52:56 PM UTC 24 9367355272 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.525343790 Aug 27 10:49:48 PM UTC 24 Aug 27 10:54:21 PM UTC 24 3485155672 ps
T881 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access.681877424 Aug 27 10:39:23 PM UTC 24 Aug 27 10:55:21 PM UTC 24 5881229274 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1622263337 Aug 27 10:39:41 PM UTC 24 Aug 27 10:55:29 PM UTC 24 8996919154 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.348456182 Aug 27 10:52:21 PM UTC 24 Aug 27 10:55:36 PM UTC 24 2897284878 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.410184914 Aug 27 10:39:59 PM UTC 24 Aug 27 10:55:48 PM UTC 24 5623685279 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2912150638 Aug 27 10:49:56 PM UTC 24 Aug 27 10:56:03 PM UTC 24 4979816312 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.4250920604 Aug 27 10:49:57 PM UTC 24 Aug 27 10:56:21 PM UTC 24 5082890000 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.996199745 Aug 27 10:49:54 PM UTC 24 Aug 27 10:56:32 PM UTC 24 6907072200 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.393366520 Aug 27 10:51:41 PM UTC 24 Aug 27 10:57:14 PM UTC 24 3220336776 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.1527115616 Aug 27 10:53:32 PM UTC 24 Aug 27 10:57:22 PM UTC 24 3504090844 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3523378828 Aug 27 10:52:05 PM UTC 24 Aug 27 10:57:47 PM UTC 24 3281933465 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3926881414 Aug 27 10:49:57 PM UTC 24 Aug 27 10:57:58 PM UTC 24 6522808266 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.608030733 Aug 27 10:52:23 PM UTC 24 Aug 27 10:58:07 PM UTC 24 3657764665 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.3521084802 Aug 27 10:50:54 PM UTC 24 Aug 27 10:58:09 PM UTC 24 4340432256 ps
T658 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.4118983911 Aug 27 10:54:56 PM UTC 24 Aug 27 10:58:51 PM UTC 24 2939272132 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.559329050 Aug 27 10:52:26 PM UTC 24 Aug 27 10:58:53 PM UTC 24 3385975544 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.3691684376 Aug 27 10:46:43 PM UTC 24 Aug 27 10:59:02 PM UTC 24 7660324328 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.4225827465 Aug 27 10:50:37 PM UTC 24 Aug 27 10:59:09 PM UTC 24 5490772328 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3763426460 Aug 27 10:51:54 PM UTC 24 Aug 27 10:59:48 PM UTC 24 4309181060 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1614645984 Aug 27 10:51:53 PM UTC 24 Aug 27 10:59:52 PM UTC 24 7728341640 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.3186747798 Aug 27 10:44:32 PM UTC 24 Aug 27 11:00:24 PM UTC 24 11197470057 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2958056898 Aug 27 10:51:52 PM UTC 24 Aug 27 11:01:06 PM UTC 24 5238261038 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2378426791 Aug 27 10:50:23 PM UTC 24 Aug 27 11:01:17 PM UTC 24 4851504180 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.555446173 Aug 27 10:57:35 PM UTC 24 Aug 27 11:01:17 PM UTC 24 3106923144 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.746774344 Aug 27 10:39:47 PM UTC 24 Aug 27 11:01:18 PM UTC 24 7523428938 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.977609184 Aug 27 10:51:20 PM UTC 24 Aug 27 11:01:19 PM UTC 24 19567075184 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.604716133 Aug 27 10:58:55 PM UTC 24 Aug 27 11:01:58 PM UTC 24 2509468972 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.608652752 Aug 27 10:39:33 PM UTC 24 Aug 27 11:02:06 PM UTC 24 9703291358 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2174462563 Aug 27 10:51:23 PM UTC 24 Aug 27 11:02:25 PM UTC 24 7388455586 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_idle.3257262422 Aug 27 10:57:31 PM UTC 24 Aug 27 11:02:41 PM UTC 24 3522940444 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.1667031705 Aug 27 10:57:59 PM UTC 24 Aug 27 11:02:47 PM UTC 24 3598386310 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.3296477030 Aug 27 10:57:20 PM UTC 24 Aug 27 11:03:08 PM UTC 24 3065740884 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_entropy.1400411935 Aug 27 10:58:31 PM UTC 24 Aug 27 11:03:12 PM UTC 24 2639476160 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1068323534 Aug 27 10:51:15 PM UTC 24 Aug 27 11:03:34 PM UTC 24 8602626150 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1910914971 Aug 27 10:57:36 PM UTC 24 Aug 27 11:03:49 PM UTC 24 3591224932 ps
T626 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.2903409819 Aug 27 11:00:31 PM UTC 24 Aug 27 11:04:01 PM UTC 24 2956994424 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_rand_baudrate.2522702672 Aug 27 10:39:14 PM UTC 24 Aug 27 11:04:31 PM UTC 24 8163479892 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.1612742440 Aug 27 10:57:35 PM UTC 24 Aug 27 11:04:47 PM UTC 24 4284710450 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.208041604 Aug 27 11:00:59 PM UTC 24 Aug 27 11:05:31 PM UTC 24 3325689148 ps
T659 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2569584129 Aug 27 10:49:59 PM UTC 24 Aug 27 11:05:54 PM UTC 24 6293711622 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2236353821 Aug 27 10:53:18 PM UTC 24 Aug 27 11:06:57 PM UTC 24 4574884024 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.2887008467 Aug 27 10:39:24 PM UTC 24 Aug 27 11:07:09 PM UTC 24 7876080820 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.3561910460 Aug 27 10:57:23 PM UTC 24 Aug 27 11:07:25 PM UTC 24 6162864678 ps
T660 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.3059959403 Aug 27 11:03:03 PM UTC 24 Aug 27 11:07:36 PM UTC 24 2678567862 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.3315764942 Aug 27 10:58:55 PM UTC 24 Aug 27 11:07:42 PM UTC 24 3098653008 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc.1827144842 Aug 27 11:02:48 PM UTC 24 Aug 27 11:07:45 PM UTC 24 2429669210 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.1666473610 Aug 27 10:51:54 PM UTC 24 Aug 27 11:07:48 PM UTC 24 5749288132 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.410857157 Aug 27 11:02:59 PM UTC 24 Aug 27 11:08:28 PM UTC 24 3149774699 ps
T882 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.3065257441 Aug 27 11:03:01 PM UTC 24 Aug 27 11:08:41 PM UTC 24 3564973140 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.3679910880 Aug 27 10:52:39 PM UTC 24 Aug 27 11:08:41 PM UTC 24 5486583928 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.94406278 Aug 27 11:05:22 PM UTC 24 Aug 27 11:09:30 PM UTC 24 2940984599 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.659692862 Aug 27 11:04:38 PM UTC 24 Aug 27 11:09:46 PM UTC 24 3250566232 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.3709100201 Aug 27 11:06:07 PM UTC 24 Aug 27 11:09:48 PM UTC 24 2571302100 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3937411980 Aug 27 10:59:57 PM UTC 24 Aug 27 11:09:52 PM UTC 24 5081049042 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.1971073419 Aug 27 10:59:56 PM UTC 24 Aug 27 11:09:52 PM UTC 24 3037589872 ps
T883 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.2812150632 Aug 27 11:05:07 PM UTC 24 Aug 27 11:10:09 PM UTC 24 3081905560 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1462844716 Aug 27 11:00:32 PM UTC 24 Aug 27 11:11:27 PM UTC 24 4520764380 ps
T884 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_idle.2379706327 Aug 27 11:06:29 PM UTC 24 Aug 27 11:11:42 PM UTC 24 2558206120 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.4265238660 Aug 27 11:09:19 PM UTC 24 Aug 27 11:12:53 PM UTC 24 2345506041 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.1013300445 Aug 27 10:46:41 PM UTC 24 Aug 27 11:13:27 PM UTC 24 10222625380 ps
T634 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_sw_mode.1026534783 Aug 27 10:59:58 PM UTC 24 Aug 27 11:14:01 PM UTC 24 4919786984 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1208905664 Aug 27 10:50:39 PM UTC 24 Aug 27 11:15:05 PM UTC 24 9472780972 ps
T885 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.610664778 Aug 27 10:50:07 PM UTC 24 Aug 27 11:16:47 PM UTC 24 11433563157 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.639068465 Aug 27 11:09:24 PM UTC 24 Aug 27 11:17:33 PM UTC 24 5089788048 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.1862806967 Aug 27 11:11:08 PM UTC 24 Aug 27 11:17:35 PM UTC 24 3075202326 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3477526800 Aug 27 10:51:21 PM UTC 24 Aug 27 11:17:39 PM UTC 24 17143348536 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1506605419 Aug 27 11:07:41 PM UTC 24 Aug 27 11:17:53 PM UTC 24 8416755946 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2702884144 Aug 27 11:07:45 PM UTC 24 Aug 27 11:18:10 PM UTC 24 4029571204 ps
T886 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2157625725 Aug 27 11:12:03 PM UTC 24 Aug 27 11:19:16 PM UTC 24 4355838816 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2813705752 Aug 27 11:08:45 PM UTC 24 Aug 27 11:19:22 PM UTC 24 6517613680 ps
T650 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.3396979698 Aug 27 10:57:32 PM UTC 24 Aug 27 11:19:36 PM UTC 24 8408541320 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.1205417435 Aug 27 11:11:06 PM UTC 24 Aug 27 11:19:37 PM UTC 24 4461181300 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1073434923 Aug 27 11:08:26 PM UTC 24 Aug 27 11:19:58 PM UTC 24 5176021610 ps
T887 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.4089629738 Aug 27 11:12:18 PM UTC 24 Aug 27 11:20:04 PM UTC 24 4954482860 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.809976528 Aug 27 11:08:48 PM UTC 24 Aug 27 11:20:22 PM UTC 24 7173715244 ps
T888 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2809343475 Aug 27 11:11:08 PM UTC 24 Aug 27 11:20:30 PM UTC 24 5090716368 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1148605060 Aug 27 10:57:28 PM UTC 24 Aug 27 11:20:47 PM UTC 24 12543553260 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.4291001180 Aug 27 11:02:46 PM UTC 24 Aug 27 11:20:51 PM UTC 24 6923759197 ps
T889 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3322311309 Aug 27 11:12:33 PM UTC 24 Aug 27 11:21:41 PM UTC 24 5431841288 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.297775746 Aug 27 10:40:03 PM UTC 24 Aug 27 11:21:42 PM UTC 24 12058982622 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3423946494 Aug 27 10:39:39 PM UTC 24 Aug 27 11:21:57 PM UTC 24 13579591695 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.4224179412 Aug 27 10:39:03 PM UTC 24 Aug 27 11:22:09 PM UTC 24 23007997464 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2470971846 Aug 27 10:46:43 PM UTC 24 Aug 27 11:22:25 PM UTC 24 34090269340 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.4098523969 Aug 27 11:08:45 PM UTC 24 Aug 27 11:22:50 PM UTC 24 8301822408 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.642885411 Aug 27 10:50:30 PM UTC 24 Aug 27 11:22:52 PM UTC 24 23017736840 ps
T890 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.4006084092 Aug 27 11:18:54 PM UTC 24 Aug 27 11:24:04 PM UTC 24 2931195513 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.1677246366 Aug 27 11:08:48 PM UTC 24 Aug 27 11:24:12 PM UTC 24 7991325642 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.917889090 Aug 27 11:11:09 PM UTC 24 Aug 27 11:24:15 PM UTC 24 4996432404 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.3757022342 Aug 27 11:02:32 PM UTC 24 Aug 27 11:24:15 PM UTC 24 6199680076 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2965663414 Aug 27 11:14:00 PM UTC 24 Aug 27 11:24:25 PM UTC 24 3850017724 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_raw_unlock.3862664032 Aug 28 12:13:41 AM UTC 24 Aug 28 12:18:49 AM UTC 24 3960291032 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.4249325481 Aug 27 11:02:45 PM UTC 24 Aug 27 11:24:37 PM UTC 24 6890857442 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3637921028 Aug 27 11:13:29 PM UTC 24 Aug 27 11:25:01 PM UTC 24 9076519697 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.993659589 Aug 27 11:14:36 PM UTC 24 Aug 27 11:25:39 PM UTC 24 4647561680 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.577213572 Aug 27 10:57:36 PM UTC 24 Aug 27 11:25:42 PM UTC 24 8222873508 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1167188181 Aug 27 11:18:54 PM UTC 24 Aug 27 11:26:08 PM UTC 24 3117385770 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1880874893 Aug 27 11:15:40 PM UTC 24 Aug 27 11:26:22 PM UTC 24 3493686396 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.1792802120 Aug 27 11:18:48 PM UTC 24 Aug 27 11:27:02 PM UTC 24 3803040594 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2644672492 Aug 27 11:03:28 PM UTC 24 Aug 27 11:27:32 PM UTC 24 7660246600 ps
T891 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4256881984 Aug 27 11:17:22 PM UTC 24 Aug 27 11:27:45 PM UTC 24 4718302240 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.677637967 Aug 27 11:20:46 PM UTC 24 Aug 27 11:28:11 PM UTC 24 7650851852 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1376711375 Aug 27 11:18:50 PM UTC 24 Aug 27 11:28:29 PM UTC 24 4123271010 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3836336469 Aug 27 11:22:46 PM UTC 24 Aug 27 11:28:38 PM UTC 24 5803368034 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1228071578 Aug 27 11:18:47 PM UTC 24 Aug 27 11:29:08 PM UTC 24 4177599048 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2785045006 Aug 27 11:25:20 PM UTC 24 Aug 27 11:29:24 PM UTC 24 3158595402 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1619247412 Aug 27 11:19:49 PM UTC 24 Aug 27 11:29:32 PM UTC 24 4787348852 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3401968703 Aug 27 11:26:22 PM UTC 24 Aug 27 11:29:35 PM UTC 24 2578965682 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.406020193 Aug 27 11:10:06 PM UTC 24 Aug 27 11:29:44 PM UTC 24 6732450762 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2512726928 Aug 27 11:23:00 PM UTC 24 Aug 27 11:29:46 PM UTC 24 5546241872 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.2714510212 Aug 27 11:23:23 PM UTC 24 Aug 27 11:29:49 PM UTC 24 3884586185 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.3384620069 Aug 27 11:20:45 PM UTC 24 Aug 27 11:29:55 PM UTC 24 4918041568 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2842143364 Aug 27 11:21:10 PM UTC 24 Aug 27 11:30:05 PM UTC 24 4314291532 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.3751510614 Aug 27 11:25:19 PM UTC 24 Aug 27 11:30:08 PM UTC 24 3041040548 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.400377902 Aug 27 11:25:20 PM UTC 24 Aug 27 11:30:14 PM UTC 24 3263658673 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1972040661 Aug 27 11:23:04 PM UTC 24 Aug 27 11:30:15 PM UTC 24 4095190657 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.4054124836 Aug 27 11:21:37 PM UTC 24 Aug 27 11:30:21 PM UTC 24 5434242712 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.955000592 Aug 27 11:25:15 PM UTC 24 Aug 27 11:30:27 PM UTC 24 3407336596 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.2922446082 Aug 27 11:22:47 PM UTC 24 Aug 27 11:30:40 PM UTC 24 4980169786 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.108819868 Aug 27 10:58:54 PM UTC 24 Aug 27 11:30:42 PM UTC 24 7907768350 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.508405749 Aug 27 10:57:59 PM UTC 24 Aug 27 11:30:50 PM UTC 24 8611439560 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.4114759551 Aug 27 11:28:21 PM UTC 24 Aug 27 11:32:29 PM UTC 24 3040739204 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.87768779 Aug 27 11:03:22 PM UTC 24 Aug 27 11:32:30 PM UTC 24 8153731850 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.3857323297 Aug 27 11:26:22 PM UTC 24 Aug 27 11:32:33 PM UTC 24 3049193560 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.838433927 Aug 27 11:22:59 PM UTC 24 Aug 27 11:32:48 PM UTC 24 5352287106 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_peri.3780199232 Aug 27 11:11:07 PM UTC 24 Aug 27 11:32:57 PM UTC 24 11325696200 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2785748366 Aug 27 10:51:52 PM UTC 24 Aug 27 11:33:11 PM UTC 24 21613585443 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2488250923 Aug 27 11:28:07 PM UTC 24 Aug 27 11:33:21 PM UTC 24 3901078075 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.3686380417 Aug 27 11:04:08 PM UTC 24 Aug 27 11:33:30 PM UTC 24 9007463658 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.3811113912 Aug 27 11:23:23 PM UTC 24 Aug 27 11:33:42 PM UTC 24 6214836964 ps
T892 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3334674003 Aug 27 11:29:15 PM UTC 24 Aug 27 11:33:56 PM UTC 24 3392638835 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.896072957 Aug 27 11:03:54 PM UTC 24 Aug 27 11:33:57 PM UTC 24 10853498848 ps
T671 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_crash_alert.2934969786 Aug 27 11:25:39 PM UTC 24 Aug 27 11:33:59 PM UTC 24 6260456064 ps
T683 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.2391734366 Aug 27 11:20:14 PM UTC 24 Aug 27 11:34:40 PM UTC 24 7794509396 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation.1223910233 Aug 27 11:03:28 PM UTC 24 Aug 27 11:36:13 PM UTC 24 9181288768 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_scrambling_smoketest.879257763 Aug 27 11:33:56 PM UTC 24 Aug 27 11:37:01 PM UTC 24 2456890026 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1111657722 Aug 27 11:26:44 PM UTC 24 Aug 27 11:37:02 PM UTC 24 4676721455 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.4142017806 Aug 27 11:24:51 PM UTC 24 Aug 27 11:37:40 PM UTC 24 8138647470 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4041537104 Aug 27 11:29:16 PM UTC 24 Aug 27 11:37:53 PM UTC 24 5441447391 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3646064418 Aug 27 11:21:11 PM UTC 24 Aug 27 11:38:29 PM UTC 24 23319815760 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.1993085438 Aug 27 11:19:58 PM UTC 24 Aug 27 11:41:32 PM UTC 24 13319505292 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.1780736136 Aug 27 11:03:54 PM UTC 24 Aug 27 11:42:02 PM UTC 24 11192595422 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.77794789 Aug 27 11:35:31 PM UTC 24 Aug 27 11:42:31 PM UTC 24 10100699380 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.2888985651 Aug 27 11:19:43 PM UTC 24 Aug 27 11:42:37 PM UTC 24 13877373784 ps
T893 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1259159975 Aug 27 11:26:58 PM UTC 24 Aug 27 11:42:38 PM UTC 24 7089423162 ps
T661 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2469732669 Aug 27 11:09:45 PM UTC 24 Aug 27 11:43:18 PM UTC 24 24287415832 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.2830831050 Aug 27 10:59:56 PM UTC 24 Aug 27 11:44:25 PM UTC 24 10664780520 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.837809354 Aug 27 11:33:54 PM UTC 24 Aug 27 11:44:28 PM UTC 24 4756993020 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1733443257 Aug 27 11:21:36 PM UTC 24 Aug 27 11:45:15 PM UTC 24 20596497684 ps
T894 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_mem_protection.904634977 Aug 27 11:34:32 PM UTC 24 Aug 27 11:51:55 PM UTC 24 5612936060 ps
T895 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1087035228 Aug 27 10:50:37 PM UTC 24 Aug 27 11:53:00 PM UTC 24 29129338475 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3311519805 Aug 27 10:52:04 PM UTC 24 Aug 27 11:53:18 PM UTC 24 20987655006 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.2338478319 Aug 27 11:24:52 PM UTC 24 Aug 27 11:53:34 PM UTC 24 16510182912 ps
T896 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_stream.2966911147 Aug 27 10:39:31 PM UTC 24 Aug 27 11:54:12 PM UTC 24 19473637608 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2386427494 Aug 27 10:52:04 PM UTC 24 Aug 27 11:57:55 PM UTC 24 17073412542 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.3928376794 Aug 27 11:29:37 PM UTC 24 Aug 27 11:57:56 PM UTC 24 24181999955 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1938038293 Aug 27 11:28:48 PM UTC 24 Aug 27 11:59:11 PM UTC 24 12062987433 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.2231560800 Aug 27 11:37:39 PM UTC 24 Aug 28 12:00:18 AM UTC 24 6177673400 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.621555495 Aug 27 10:52:26 PM UTC 24 Aug 28 12:04:26 AM UTC 24 19178422013 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.176086425 Aug 27 10:39:34 PM UTC 24 Aug 28 12:09:53 AM UTC 24 42308561915 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.2113391279 Aug 28 12:10:30 AM UTC 24 Aug 28 12:13:05 AM UTC 24 1930599423 ps
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T455 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.983727170 Aug 27 11:37:43 PM UTC 24 Aug 28 12:33:08 AM UTC 24 11994557480 ps
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T53 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.76323966 Aug 27 11:39:13 PM UTC 24 Aug 28 12:37:09 AM UTC 24 14425413982 ps
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T914 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_manufacturer.225585390 Aug 28 12:39:28 AM UTC 24 Aug 28 12:42:46 AM UTC 24 3093305310 ps
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T290 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.3853729934 Aug 27 11:33:03 PM UTC 24 Aug 28 12:42:56 AM UTC 24 30294088364 ps
T662 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_exception_c.2732218545 Aug 27 11:33:35 PM UTC 24 Aug 28 12:43:26 AM UTC 24 14804262375 ps
T916 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_smoke.504733573 Aug 27 11:35:57 PM UTC 24 Aug 28 12:43:33 AM UTC 24 14734258680 ps
T917 /workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_smoketest.2925897478 Aug 28 12:37:58 AM UTC 24 Aug 28 12:44:12 AM UTC 24 3349330320 ps
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