Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	134737	1			T95	3		T96	9		T97	6
values[2]	8393	1			T188	1		T271	2		T272	1
values[3]	2958	1			T644	1		T480	8		T540	28
values[4]	1780	1			T540	14		T542	112		T472	61
values[5]	1106	1			T540	7		T542	121		T472	29
values[6]	714	1			T542	47		T472	11		T622	3
values[7]	507	1			T542	15		T472	1		T622	1
values[8]	433	1			T542	9		T622	5		T508	14
values[9]	407	1			T542	9		T622	1		T508	6
values[10]	282	1			T542	2		T508	5		T541	10
values[11]	271	1			T508	4		T541	5		T527	7
values[12]	231	1			T508	4		T541	3		T527	3
values[13]	243	1			T508	6		T541	9		T512	4
values[14]	267	1			T508	3		T541	6		T512	5
values[15]	305	1			T508	9		T541	9		T512	18
values[16]	221	1			T508	3		T541	9		T512	10
values[17]	224	1			T508	23		T541	7		T512	4
values[18]	228	1			T508	7		T541	5		T512	4
values[19]	251	1			T508	5		T541	3		T512	3
values[20]	193	1			T508	7		T541	5		T512	5
values[21]	225	1			T508	12		T541	6		T512	5
values[22]	246	1			T508	12		T541	20		T512	8
values[23]	214	1			T508	3		T541	9		T512	14
values[24]	281	1			T508	7		T541	4		T512	21
values[25]	231	1			T508	5		T541	5		T512	4
values[26]	208	1			T508	3		T541	4		T512	14
values[27]	202	1			T508	3		T541	4		T512	7
values[28]	197	1			T508	4		T541	4		T512	2
values[29]	234	1			T508	3		T541	6		T512	5
values[30]	269	1			T508	4		T541	11		T512	14
values[31]	212	1			T508	5		T541	4		T512	2
values[32]	247	1			T508	9		T541	16		T512	8
values[33]	241	1			T508	6		T541	6		T512	14
values[34]	236	1			T508	10		T541	12		T512	6
values[35]	226	1			T508	22		T541	6		T512	5
values[36]	226	1			T508	11		T541	15		T512	7
values[37]	204	1			T508	6		T541	13		T512	6
values[38]	185	1			T508	3		T541	7		T512	6
values[39]	203	1			T508	8		T541	9		T512	7
values[40]	241	1			T508	11		T541	4		T512	6
values[41]	258	1			T508	9		T541	4		T512	13
values[42]	231	1			T508	5		T541	4		T512	7
values[43]	203	1			T508	6		T541	7		T512	14
values[44]	184	1			T508	10		T541	4		T512	5
values[45]	192	1			T508	3		T541	3		T512	7
values[46]	230	1			T508	6		T541	5		T512	11
values[47]	233	1			T508	2		T541	3		T512	5
values[48]	221	1			T508	4		T541	5		T512	7
values[49]	192	1			T508	3		T541	8		T512	9
values[50]	225	1			T508	8		T541	26		T512	5
values[51]	197	1			T508	4		T541	5		T512	7
values[52]	222	1			T508	10		T541	5		T512	13
values[53]	175	1			T508	3		T541	10		T512	5
values[54]	172	1			T508	6		T541	8		T512	5
values[55]	172	1			T508	6		T541	7		T512	4
values[56]	200	1			T508	15		T541	14		T512	5
values[57]	205	1			T508	14		T541	22		T512	7
values[58]	194	1			T508	12		T541	6		T512	23
values[59]	186	1			T508	7		T541	5		T512	8
values[60]	174	1			T508	2		T541	6		T512	15
values[61]	161	1			T541	6		T512	7		T539	5
values[62]	135	1			T541	4		T539	1		T805	1
values[63]	176	1			T541	4		T539	4		T805	1
values[64]	174	1			T541	4		T539	2		T805	1
values[65]	171	1			T541	5		T539	9		T805	1
values[66]	139	1			T541	2		T539	10		T805	1
values[67]	138	1			T541	3		T539	8		T805	1
values[68]	139	1			T541	5		T539	1		T805	1
values[69]	131	1			T539	1		T805	1		T496	1
values[70]	114	1			T539	2		T805	1		T496	1
values[71]	104	1			T539	2		T805	1		T496	1
values[72]	111	1			T539	1		T805	1		T496	1
values[73]	113	1			T539	2		T805	1		T496	1
values[74]	136	1			T539	4		T805	1		T496	1
values[75]	95	1			T539	2		T805	1		T496	1
values[76]	88	1			T539	5		T805	1		T496	1
values[77]	90	1			T539	10		T805	1		T496	1
values[78]	74	1			T539	8		T805	1		T496	1
values[79]	81	1			T539	1		T805	1		T496	1
values[80]	68	1			T539	1		T805	1		T496	1
values[81]	70	1			T539	3		T805	1		T496	1
values[82]	76	1			T539	1		T805	1		T496	1
values[83]	81	1			T539	4		T805	1		T496	1
values[84]	75	1			T539	1		T805	1		T496	1
values[85]	74	1			T539	1		T805	1		T496	1
values[86]	61	1			T539	3		T805	1		T496	1
values[87]	105	1			T539	1		T805	1		T496	1
values[88]	97	1			T539	5		T805	1		T496	1
values[89]	96	1			T539	9		T805	1		T496	1
values[90]	82	1			T539	7		T805	1		T496	1
values[91]	77	1			T539	4		T805	1		T496	1
values[92]	79	1			T539	3		T805	1		T496	1
values[93]	95	1			T539	4		T805	1		T496	1
values[94]	100	1			T539	10		T805	1		T496	1
values[95]	102	1			T539	8		T805	1		T496	1
values[96]	95	1			T539	14		T805	1		T496	1
values[97]	75	1			T539	11		T805	1		T496	1
values[98]	91	1			T539	3		T805	1		T496	1
values[99]	81	1			T539	2		T805	1		T496	1
values[100]	88	1			T539	6		T805	1		T496	1
values[101]	78	1			T539	4		T805	1		T496	1
values[102]	84	1			T539	3		T805	1		T496	1
values[103]	71	1			T539	2		T805	1		T496	1
values[104]	75	1			T539	2		T805	1		T496	1
values[105]	76	1			T539	3		T805	1		T496	1
values[106]	73	1			T539	5		T805	1		T496	1
values[107]	66	1			T539	1		T805	1		T496	1
values[108]	75	1			T539	3		T805	1		T496	1
values[109]	77	1			T539	6		T805	1		T496	1
values[110]	74	1			T539	5		T805	1		T496	1
values[111]	71	1			T539	10		T805	1		T496	1
values[112]	78	1			T539	9		T805	1		T496	1
values[113]	71	1			T539	4		T805	2		T496	1
values[114]	59	1			T539	1		T805	3		T496	6
values[115]	69	1			T539	3		T805	1		T496	2
values[116]	54	1			T539	3		T805	3		T496	1
values[117]	51	1			T539	1		T805	1		T496	2
values[118]	58	1			T539	3		T805	1		T496	3
values[119]	51	1			T539	4		T805	2		T496	1
values[120]	60	1			T539	4		T805	2		T496	1
values[121]	45	1			T539	2		T805	5		T496	3
values[122]	63	1			T539	3		T805	2		T496	2
values[123]	51	1			T539	1		T805	2		T496	3
values[124]	67	1			T539	5		T805	1		T496	1
values[125]	86	1			T539	5		T805	4		T496	7
values[126]	159	1			T539	12		T805	1		T496	3
values[127]	885	1			T539	18		T805	22		T496	40
values[128]	6857	1			T539	7		T805	307		T496	367