Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.pattgen_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	137651	1			T95	8		T96	7		T101	2
values[2]	10308	1			T478	1		T460	4		T458	4
values[3]	3941	1			T558	25		T644	201		T477	104
values[4]	2082	1			T558	4		T644	107		T477	76
values[5]	1386	1			T644	37		T477	55		T534	2
values[6]	912	1			T644	12		T477	34		T534	5
values[7]	752	1			T644	3		T477	25		T534	5
values[8]	600	1			T644	2		T477	5		T534	1
values[9]	426	1			T477	10		T534	3		T648	4
values[10]	459	1			T477	26		T534	1		T648	14
values[11]	488	1			T477	24		T534	8		T648	10
values[12]	440	1			T477	10		T534	7		T648	5
values[13]	319	1			T477	4		T534	3		T648	3
values[14]	387	1			T534	3		T648	10		T514	16
values[15]	342	1			T534	4		T648	12		T514	7
values[16]	393	1			T534	8		T648	15		T514	4
values[17]	384	1			T534	3		T648	9		T514	3
values[18]	378	1			T534	3		T648	3		T514	7
values[19]	385	1			T534	2		T648	13		T514	10
values[20]	331	1			T534	3		T648	4		T514	12
values[21]	282	1			T534	2		T648	7		T514	5
values[22]	295	1			T534	1		T648	3		T514	7
values[23]	329	1			T534	2		T648	5		T514	6
values[24]	331	1			T534	2		T648	4		T514	4
values[25]	319	1			T534	3		T648	8		T514	7
values[26]	339	1			T534	3		T648	14		T514	5
values[27]	315	1			T534	7		T648	15		T514	6
values[28]	318	1			T534	5		T648	5		T514	4
values[29]	317	1			T534	1		T648	13		T514	7
values[30]	360	1			T534	2		T648	4		T514	6
values[31]	364	1			T534	2		T648	3		T514	11
values[32]	298	1			T534	1		T648	5		T514	9
values[33]	310	1			T534	1		T648	5		T514	9
values[34]	400	1			T534	2		T648	8		T514	20
values[35]	317	1			T534	3		T648	4		T514	4
values[36]	284	1			T534	4		T648	3		T514	4
values[37]	298	1			T534	2		T648	11		T514	4
values[38]	278	1			T534	2		T648	6		T514	8
values[39]	287	1			T534	1		T648	13		T514	4
values[40]	305	1			T534	5		T648	4		T514	19
values[41]	304	1			T534	1		T648	19		T514	11
values[42]	292	1			T534	3		T648	22		T514	9
values[43]	289	1			T534	3		T648	3		T514	4
values[44]	305	1			T534	7		T648	12		T514	5
values[45]	249	1			T534	1		T648	3		T514	3
values[46]	285	1			T534	2		T648	4		T514	4
values[47]	330	1			T534	5		T648	3		T514	3
values[48]	296	1			T534	7		T648	10		T514	4
values[49]	285	1			T534	2		T648	8		T514	12
values[50]	275	1			T534	1		T648	7		T514	10
values[51]	268	1			T534	1		T648	18		T514	2
values[52]	245	1			T534	1		T648	16		T514	5
values[53]	237	1			T534	2		T648	7		T514	7
values[54]	266	1			T534	1		T648	7		T514	9
values[55]	259	1			T534	3		T648	9		T514	3
values[56]	250	1			T534	2		T648	6		T514	11
values[57]	226	1			T534	3		T648	3		T514	2
values[58]	240	1			T534	4		T648	6		T514	6
values[59]	240	1			T534	1		T648	4		T514	4
values[60]	219	1			T534	3		T648	6		T514	10
values[61]	192	1			T534	1		T648	1		T514	6
values[62]	172	1			T534	1		T514	11		T607	1
values[63]	159	1			T534	2		T514	3		T607	5
values[64]	131	1			T534	1		T514	5		T607	11
values[65]	135	1			T534	3		T607	11		T789	1
values[66]	147	1			T534	2		T607	13		T789	1
values[67]	120	1			T534	3		T607	4		T789	1
values[68]	146	1			T534	3		T607	2		T789	1
values[69]	136	1			T534	2		T607	2		T789	1
values[70]	122	1			T534	6		T607	2		T789	1
values[71]	177	1			T534	11		T607	4		T789	1
values[72]	131	1			T534	2		T607	9		T789	1
values[73]	133	1			T534	1		T607	1		T789	1
values[74]	144	1			T534	1		T607	4		T789	1
values[75]	119	1			T534	2		T607	11		T789	1
values[76]	118	1			T534	2		T607	5		T789	1
values[77]	119	1			T534	1		T607	3		T789	1
values[78]	120	1			T534	1		T607	6		T789	1
values[79]	115	1			T534	2		T607	2		T789	1
values[80]	115	1			T534	3		T607	7		T789	1
values[81]	125	1			T534	2		T607	5		T789	1
values[82]	92	1			T534	2		T607	6		T789	1
values[83]	101	1			T534	1		T607	1		T789	1
values[84]	111	1			T534	3		T607	2		T789	1
values[85]	90	1			T534	2		T607	1		T789	1
values[86]	82	1			T534	4		T607	2		T789	1
values[87]	78	1			T534	3		T607	2		T789	1
values[88]	94	1			T534	10		T607	3		T789	1
values[89]	98	1			T534	7		T607	1		T789	1
values[90]	100	1			T534	7		T607	5		T789	1
values[91]	90	1			T534	5		T607	9		T789	1
values[92]	112	1			T534	6		T607	13		T789	1
values[93]	109	1			T534	6		T607	13		T789	1
values[94]	79	1			T534	6		T607	13		T789	1
values[95]	117	1			T534	10		T607	11		T789	1
values[96]	86	1			T534	4		T607	3		T789	1
values[97]	95	1			T534	3		T607	6		T789	1
values[98]	94	1			T534	1		T607	7		T789	1
values[99]	98	1			T534	6		T607	3		T789	1
values[100]	68	1			T534	4		T607	1		T789	2
values[101]	94	1			T534	5		T607	5		T789	2
values[102]	97	1			T534	2		T607	3		T789	1
values[103]	100	1			T534	6		T607	3		T789	1
values[104]	113	1			T534	8		T607	6		T789	1
values[105]	128	1			T534	8		T607	3		T789	2
values[106]	90	1			T534	7		T607	3		T789	2
values[107]	95	1			T534	6		T607	11		T789	1
values[108]	127	1			T534	5		T607	8		T789	6
values[109]	89	1			T534	1		T607	3		T789	1
values[110]	95	1			T534	2		T607	9		T789	2
values[111]	86	1			T534	3		T607	3		T789	3
values[112]	86	1			T534	8		T607	2		T789	1
values[113]	85	1			T534	2		T789	1		T822	1
values[114]	95	1			T534	2		T789	3		T822	2
values[115]	103	1			T534	1		T789	5		T822	1
values[116]	102	1			T534	2		T789	1		T822	4
values[117]	105	1			T534	7		T789	1		T822	3
values[118]	99	1			T534	5		T789	1		T822	2
values[119]	88	1			T534	3		T789	1		T822	3
values[120]	87	1			T534	2		T789	1		T822	2
values[121]	77	1			T534	2		T789	1		T822	2
values[122]	82	1			T534	2		T789	1		T822	2
values[123]	110	1			T534	11		T789	2		T822	4
values[124]	90	1			T534	1		T789	2		T822	9
values[125]	110	1			T534	3		T789	3		T822	10
values[126]	137	1			T534	1		T789	1		T822	26
values[127]	966	1			T534	13		T789	39		T822	88
values[128]	7880	1			T534	8		T789	332		T822	50