Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	149695	1			T95	8		T96	2		T97	2
values[2]	4151	1			T272	1		T458	4		T550	2
values[3]	2121	1			T550	2		T686	32		T477	32
values[4]	1550	1			T550	1		T686	50		T477	31
values[5]	1239	1			T550	2		T686	30		T477	35
values[6]	1087	1			T550	4		T686	41		T477	31
values[7]	845	1			T550	3		T686	32		T477	46
values[8]	789	1			T550	8		T686	17		T477	38
values[9]	786	1			T550	4		T686	3		T477	54
values[10]	723	1			T550	5		T686	2		T477	76
values[11]	707	1			T550	1		T686	7		T477	64
values[12]	689	1			T550	1		T686	12		T477	32
values[13]	667	1			T550	2		T686	5		T477	31
values[14]	564	1			T550	1		T686	11		T477	41
values[15]	584	1			T550	2		T686	5		T477	43
values[16]	559	1			T550	2		T686	5		T477	51
values[17]	506	1			T550	3		T686	9		T477	32
values[18]	405	1			T550	2		T686	7		T477	15
values[19]	355	1			T550	1		T686	2		T477	11
values[20]	360	1			T550	3		T686	4		T477	11
values[21]	333	1			T550	1		T686	3		T477	7
values[22]	296	1			T550	4		T686	10		T477	6
values[23]	279	1			T550	4		T686	6		T477	7
values[24]	316	1			T550	2		T686	15		T477	14
values[25]	306	1			T550	3		T686	22		T477	26
values[26]	273	1			T550	1		T686	19		T477	30
values[27]	250	1			T550	2		T686	19		T477	31
values[28]	246	1			T550	2		T686	22		T477	34
values[29]	251	1			T550	3		T686	11		T477	28
values[30]	147	1			T550	1		T686	12		T477	9
values[31]	146	1			T550	2		T686	8		T807	1
values[32]	168	1			T550	1		T686	13		T807	1
values[33]	150	1			T550	4		T686	12		T807	1
values[34]	132	1			T550	5		T686	4		T807	1
values[35]	153	1			T550	2		T686	4		T807	1
values[36]	143	1			T550	4		T807	1		T796	1
values[37]	122	1			T550	2		T807	1		T796	1
values[38]	103	1			T550	3		T807	1		T796	1
values[39]	106	1			T550	3		T807	1		T796	1
values[40]	84	1			T550	5		T807	1		T796	1
values[41]	69	1			T550	4		T807	1		T796	1
values[42]	59	1			T550	2		T807	1		T796	1
values[43]	75	1			T550	3		T807	1		T796	1
values[44]	68	1			T550	2		T807	1		T796	1
values[45]	61	1			T550	3		T807	1		T796	1
values[46]	108	1			T550	1		T807	1		T796	1
values[47]	95	1			T550	2		T807	1		T796	1
values[48]	73	1			T550	2		T807	1		T796	1
values[49]	69	1			T550	2		T807	1		T796	1
values[50]	69	1			T550	4		T807	1		T796	1
values[51]	73	1			T550	2		T807	1		T796	1
values[52]	74	1			T550	2		T807	1		T796	1
values[53]	82	1			T550	1		T807	1		T796	1
values[54]	68	1			T550	4		T807	1		T796	1
values[55]	52	1			T550	5		T807	1		T796	1
values[56]	49	1			T550	3		T807	1		T796	1
values[57]	37	1			T550	3		T807	1		T796	1
values[58]	41	1			T550	3		T807	1		T796	1
values[59]	54	1			T550	3		T807	1		T796	1
values[60]	51	1			T550	1		T807	1		T796	1
values[61]	60	1			T550	2		T807	1		T796	1
values[62]	53	1			T550	4		T807	1		T796	1
values[63]	56	1			T550	2		T807	1		T796	1
values[64]	55	1			T550	3		T807	1		T796	1
values[65]	56	1			T550	2		T807	1		T796	1
values[66]	50	1			T550	4		T807	1		T796	1
values[67]	50	1			T550	4		T807	1		T796	1
values[68]	43	1			T550	1		T807	1		T796	1
values[69]	44	1			T550	1		T807	1		T796	1
values[70]	41	1			T550	3		T807	1		T796	1
values[71]	43	1			T550	1		T807	1		T796	1
values[72]	55	1			T550	2		T807	1		T796	1
values[73]	46	1			T550	2		T807	1		T796	1
values[74]	53	1			T550	1		T807	1		T796	1
values[75]	43	1			T550	2		T807	1		T796	1
values[76]	43	1			T550	1		T807	1		T796	1
values[77]	56	1			T550	1		T807	1		T796	1
values[78]	50	1			T550	1		T807	1		T796	1
values[79]	58	1			T550	1		T807	1		T796	2
values[80]	52	1			T550	2		T807	1		T796	1
values[81]	43	1			T550	1		T807	1		T796	1
values[82]	47	1			T550	2		T807	1		T796	1
values[83]	51	1			T550	1		T807	1		T796	2
values[84]	67	1			T550	4		T807	1		T796	4
values[85]	60	1			T550	3		T807	1		T796	6
values[86]	50	1			T550	1		T807	1		T796	6
values[87]	51	1			T550	2		T807	1		T796	1
values[88]	47	1			T550	1		T807	1		T796	1
values[89]	47	1			T550	1		T807	1		T796	2
values[90]	64	1			T550	4		T807	1		T796	6
values[91]	66	1			T550	2		T807	1		T796	6
values[92]	56	1			T550	3		T807	1		T796	2
values[93]	53	1			T550	1		T807	1		T796	2
values[94]	53	1			T550	2		T807	1		T796	1
values[95]	57	1			T550	2		T807	1		T796	2
values[96]	57	1			T550	1		T807	1		T796	2
values[97]	57	1			T550	3		T807	1		T796	2
values[98]	65	1			T550	2		T807	1		T796	2
values[99]	76	1			T550	2		T807	1		T796	3
values[100]	67	1			T550	4		T807	1		T796	1
values[101]	79	1			T550	2		T807	1		T796	3
values[102]	73	1			T550	1		T807	1		T796	2
values[103]	73	1			T550	2		T807	1		T796	3
values[104]	73	1			T550	5		T807	1		T796	2
values[105]	72	1			T550	1		T807	2		T796	1
values[106]	85	1			T550	2		T807	2		T796	4
values[107]	93	1			T550	2		T807	2		T796	3
values[108]	96	1			T550	7		T807	2		T796	2
values[109]	92	1			T550	3		T807	2		T796	1
values[110]	103	1			T550	3		T807	2		T796	2
values[111]	99	1			T550	6		T807	1		T796	3
values[112]	98	1			T550	8		T807	2		T796	3
values[113]	78	1			T550	4		T807	3		T796	1
values[114]	91	1			T550	5		T807	3		T796	3
values[115]	79	1			T550	5		T807	3		T796	1
values[116]	87	1			T550	6		T807	1		T796	3
values[117]	78	1			T550	9		T807	2		T796	1
values[118]	81	1			T550	3		T807	1		T796	3
values[119]	91	1			T550	9		T807	1		T796	3
values[120]	82	1			T550	7		T807	2		T796	1
values[121]	78	1			T550	3		T807	4		T796	1
values[122]	89	1			T550	1		T807	7		T796	1
values[123]	124	1			T550	3		T807	1		T796	2
values[124]	163	1			T550	5		T807	1		T796	1
values[125]	334	1			T550	21		T807	1		T796	1
values[126]	713	1			T550	63		T807	14		T796	2
values[127]	2535	1			T550	39		T807	114		T796	100
values[128]	4660	1			T550	3		T807	246		T796	221