Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	150420	1			T95	6		T96	6		T97	1
values[2]	5283	1			T478	1		T565	1		T458	7
values[3]	2738	1			T550	1		T826	30		T482	1
values[4]	2030	1			T550	2		T826	22		T482	2
values[5]	1612	1			T550	3		T826	39		T482	3
values[6]	1332	1			T550	1		T826	29		T482	4
values[7]	1072	1			T550	3		T826	28		T482	1
values[8]	940	1			T550	1		T826	23		T482	3
values[9]	831	1			T550	1		T826	16		T482	1
values[10]	702	1			T550	3		T826	22		T482	3
values[11]	580	1			T550	3		T826	17		T482	1
values[12]	508	1			T550	2		T826	18		T482	2
values[13]	495	1			T550	1		T826	26		T482	2
values[14]	550	1			T550	2		T826	43		T482	1
values[15]	539	1			T550	1		T826	35		T482	1
values[16]	574	1			T550	3		T826	33		T482	3
values[17]	534	1			T550	4		T826	21		T482	2
values[18]	432	1			T550	2		T826	7		T482	1
values[19]	398	1			T550	2		T826	1		T482	1
values[20]	436	1			T550	5		T482	3		T824	1
values[21]	428	1			T550	3		T482	2		T824	1
values[22]	392	1			T550	4		T482	3		T824	1
values[23]	345	1			T550	3		T482	3		T824	1
values[24]	312	1			T550	2		T482	1		T824	1
values[25]	274	1			T550	7		T482	2		T824	1
values[26]	248	1			T550	3		T482	4		T824	1
values[27]	233	1			T550	3		T482	4		T824	1
values[28]	178	1			T550	1		T482	2		T824	1
values[29]	204	1			T550	3		T482	2		T824	1
values[30]	200	1			T550	2		T482	1		T824	1
values[31]	192	1			T550	2		T482	2		T824	1
values[32]	174	1			T550	5		T482	3		T824	1
values[33]	140	1			T550	1		T482	2		T824	1
values[34]	110	1			T550	2		T482	3		T824	1
values[35]	96	1			T550	3		T482	1		T824	1
values[36]	82	1			T550	2		T482	2		T824	1
values[37]	84	1			T550	3		T482	1		T824	1
values[38]	79	1			T550	2		T482	4		T824	1
values[39]	116	1			T550	2		T482	2		T824	1
values[40]	136	1			T550	6		T482	1		T824	1
values[41]	142	1			T550	4		T482	5		T824	1
values[42]	133	1			T550	6		T482	3		T824	1
values[43]	151	1			T550	3		T482	4		T824	1
values[44]	134	1			T550	4		T482	1		T824	1
values[45]	105	1			T550	2		T482	1		T824	1
values[46]	132	1			T550	2		T482	1		T824	1
values[47]	110	1			T550	2		T482	2		T824	1
values[48]	73	1			T550	2		T482	1		T824	1
values[49]	63	1			T550	2		T482	1		T824	1
values[50]	72	1			T550	3		T482	3		T824	1
values[51]	85	1			T550	1		T482	2		T824	1
values[52]	75	1			T550	1		T482	1		T824	1
values[53]	82	1			T550	2		T482	2		T824	1
values[54]	67	1			T550	3		T482	1		T824	1
values[55]	74	1			T550	2		T482	1		T824	1
values[56]	60	1			T550	2		T482	3		T824	1
values[57]	57	1			T550	7		T482	1		T824	1
values[58]	61	1			T550	2		T482	2		T824	1
values[59]	64	1			T550	1		T482	7		T824	1
values[60]	57	1			T550	2		T482	5		T824	1
values[61]	62	1			T550	2		T482	4		T824	1
values[62]	60	1			T550	3		T482	4		T824	1
values[63]	56	1			T550	4		T482	3		T824	1
values[64]	69	1			T550	1		T482	1		T824	1
values[65]	70	1			T550	3		T482	2		T824	1
values[66]	73	1			T550	3		T482	3		T824	1
values[67]	72	1			T550	2		T482	3		T824	1
values[68]	65	1			T550	2		T482	6		T824	1
values[69]	53	1			T550	1		T482	2		T824	1
values[70]	66	1			T550	4		T482	2		T824	1
values[71]	53	1			T550	1		T482	1		T824	1
values[72]	70	1			T550	2		T482	3		T824	1
values[73]	63	1			T550	1		T482	4		T824	1
values[74]	78	1			T550	3		T482	7		T824	1
values[75]	66	1			T550	5		T482	2		T824	1
values[76]	67	1			T550	5		T482	3		T824	1
values[77]	63	1			T550	1		T482	6		T824	1
values[78]	82	1			T550	3		T482	5		T824	1
values[79]	67	1			T550	3		T482	2		T824	1
values[80]	68	1			T550	4		T482	4		T824	1
values[81]	55	1			T550	1		T482	1		T824	1
values[82]	70	1			T550	1		T482	1		T824	1
values[83]	85	1			T550	4		T482	2		T824	1
values[84]	89	1			T550	2		T482	2		T824	1
values[85]	104	1			T550	1		T482	1		T824	1
values[86]	74	1			T550	4		T482	2		T824	1
values[87]	80	1			T550	3		T482	2		T824	1
values[88]	89	1			T550	2		T482	3		T824	1
values[89]	77	1			T550	2		T482	1		T824	1
values[90]	81	1			T550	5		T482	4		T824	1
values[91]	79	1			T550	2		T482	3		T824	1
values[92]	64	1			T550	2		T482	3		T824	1
values[93]	65	1			T550	1		T482	2		T824	1
values[94]	73	1			T550	2		T482	1		T824	1
values[95]	84	1			T550	1		T482	2		T824	1
values[96]	83	1			T550	4		T482	1		T824	1
values[97]	87	1			T550	1		T482	2		T824	1
values[98]	77	1			T550	2		T482	1		T824	1
values[99]	88	1			T550	2		T482	1		T824	1
values[100]	76	1			T550	4		T482	1		T824	1
values[101]	92	1			T550	8		T482	3		T824	1
values[102]	101	1			T550	8		T482	2		T824	1
values[103]	85	1			T550	2		T482	6		T824	1
values[104]	66	1			T550	3		T482	5		T824	1
values[105]	72	1			T550	3		T482	3		T824	1
values[106]	85	1			T550	2		T482	3		T824	1
values[107]	114	1			T550	4		T482	3		T824	1
values[108]	93	1			T550	5		T482	1		T824	1
values[109]	89	1			T550	9		T482	3		T824	1
values[110]	107	1			T550	8		T482	3		T824	1
values[111]	106	1			T550	7		T482	3		T824	1
values[112]	91	1			T550	6		T482	1		T824	2
values[113]	98	1			T550	11		T482	2		T824	6
values[114]	105	1			T550	5		T482	4		T824	2
values[115]	110	1			T550	4		T482	7		T824	5
values[116]	116	1			T550	5		T482	12		T824	4
values[117]	108	1			T550	3		T482	7		T824	1
values[118]	94	1			T550	3		T482	4		T824	2
values[119]	101	1			T550	4		T482	2		T824	4
values[120]	94	1			T550	5		T482	4		T824	2
values[121]	99	1			T550	2		T482	2		T824	3
values[122]	126	1			T550	4		T482	3		T824	7
values[123]	119	1			T550	4		T482	14		T824	2
values[124]	185	1			T550	12		T482	25		T824	2
values[125]	322	1			T550	15		T482	45		T824	2
values[126]	760	1			T550	33		T482	76		T824	15
values[127]	2972	1			T550	20		T482	50		T824	83
values[128]	5401	1			T550	2		T482	9		T824	166