Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	177754	1			T95	5		T96	4		T97	9
values[2]	5027	1			T272	3		T559	2		T460	1
values[3]	2065	1			T550	16		T482	26		T644	8
values[4]	1512	1			T550	15		T482	20		T644	5
values[5]	1137	1			T550	27		T482	11		T644	2
values[6]	1013	1			T550	32		T482	16		T644	1
values[7]	924	1			T550	42		T482	10		T644	2
values[8]	806	1			T550	51		T482	22		T644	2
values[9]	761	1			T550	56		T482	26		T644	2
values[10]	678	1			T550	26		T482	25		T644	2
values[11]	639	1			T550	31		T482	37		T644	2
values[12]	568	1			T550	29		T482	42		T644	2
values[13]	502	1			T550	32		T482	41		T644	9
values[14]	508	1			T550	57		T482	31		T644	4
values[15]	440	1			T550	29		T482	32		T644	3
values[16]	418	1			T550	13		T482	29		T644	5
values[17]	422	1			T550	8		T482	10		T644	8
values[18]	375	1			T550	2		T482	4		T644	10
values[19]	339	1			T482	9		T644	6		T540	3
values[20]	294	1			T482	9		T644	1		T540	3
values[21]	282	1			T644	1		T540	3		T798	4
values[22]	255	1			T644	4		T540	2		T798	21
values[23]	250	1			T644	2		T540	1		T798	23
values[24]	263	1			T644	3		T540	2		T798	16
values[25]	330	1			T644	3		T540	4		T798	28
values[26]	301	1			T644	1		T540	4		T798	19
values[27]	207	1			T644	2		T540	1		T798	15
values[28]	192	1			T644	6		T540	1		T798	24
values[29]	227	1			T644	2		T540	3		T798	37
values[30]	236	1			T644	3		T540	3		T798	44
values[31]	203	1			T644	2		T540	1		T798	26
values[32]	146	1			T644	2		T540	2		T798	17
values[33]	117	1			T644	4		T540	2		T798	7
values[34]	111	1			T644	4		T540	3		T798	13
values[35]	154	1			T644	5		T540	3		T798	24
values[36]	168	1			T644	1		T540	2		T798	21
values[37]	161	1			T644	1		T540	2		T798	11
values[38]	171	1			T644	2		T540	3		T798	7
values[39]	134	1			T644	4		T540	3		T798	2
values[40]	87	1			T644	1		T540	3		T788	1
values[41]	71	1			T644	2		T540	2		T788	1
values[42]	67	1			T644	4		T540	1		T788	1
values[43]	75	1			T644	2		T540	8		T788	1
values[44]	56	1			T644	2		T540	8		T788	1
values[45]	49	1			T644	1		T540	3		T788	1
values[46]	52	1			T644	4		T540	2		T788	1
values[47]	43	1			T644	2		T540	1		T788	1
values[48]	41	1			T644	3		T540	3		T788	1
values[49]	41	1			T644	1		T540	5		T788	1
values[50]	41	1			T644	5		T540	7		T788	1
values[51]	31	1			T644	4		T540	1		T788	1
values[52]	48	1			T644	11		T540	4		T788	1
values[53]	40	1			T644	10		T540	1		T788	1
values[54]	48	1			T644	2		T540	3		T788	1
values[55]	47	1			T644	2		T540	2		T788	1
values[56]	44	1			T644	2		T540	3		T788	1
values[57]	43	1			T644	6		T540	1		T788	1
values[58]	34	1			T644	3		T540	1		T788	1
values[59]	40	1			T644	2		T540	6		T788	1
values[60]	47	1			T644	4		T540	6		T788	2
values[61]	39	1			T644	3		T540	3		T788	1
values[62]	48	1			T644	4		T540	1		T788	1
values[63]	41	1			T644	2		T540	3		T788	1
values[64]	44	1			T644	5		T540	1		T788	1
values[65]	46	1			T644	1		T540	1		T788	1
values[66]	45	1			T644	6		T540	1		T788	1
values[67]	39	1			T644	3		T540	2		T788	1
values[68]	40	1			T644	4		T540	2		T788	1
values[69]	38	1			T644	4		T540	3		T788	1
values[70]	46	1			T644	2		T540	5		T788	1
values[71]	45	1			T644	3		T540	3		T788	1
values[72]	45	1			T644	7		T540	3		T788	1
values[73]	44	1			T644	3		T540	2		T788	1
values[74]	46	1			T644	3		T540	4		T788	1
values[75]	52	1			T644	1		T540	4		T788	1
values[76]	56	1			T644	1		T540	9		T788	1
values[77]	49	1			T644	1		T540	2		T788	1
values[78]	51	1			T644	4		T540	1		T788	1
values[79]	43	1			T644	1		T540	2		T788	1
values[80]	49	1			T644	4		T540	5		T788	1
values[81]	50	1			T644	3		T540	5		T788	1
values[82]	49	1			T644	6		T540	3		T788	1
values[83]	51	1			T644	5		T540	1		T788	1
values[84]	53	1			T644	9		T540	2		T788	2
values[85]	42	1			T644	6		T540	2		T788	3
values[86]	52	1			T644	8		T540	2		T788	3
values[87]	67	1			T644	8		T540	1		T788	2
values[88]	55	1			T644	6		T540	3		T788	2
values[89]	43	1			T644	4		T540	4		T788	2
values[90]	53	1			T644	6		T540	1		T788	3
values[91]	51	1			T644	4		T540	1		T788	4
values[92]	70	1			T644	2		T540	2		T788	4
values[93]	66	1			T644	6		T540	1		T788	4
values[94]	65	1			T644	5		T540	2		T788	2
values[95]	64	1			T644	5		T540	8		T788	2
values[96]	62	1			T644	4		T540	4		T788	3
values[97]	52	1			T644	3		T540	8		T788	2
values[98]	45	1			T644	3		T540	3		T788	2
values[99]	63	1			T644	2		T540	4		T788	4
values[100]	61	1			T644	4		T540	1		T788	1
values[101]	82	1			T644	6		T540	3		T788	4
values[102]	65	1			T644	5		T540	3		T788	7
values[103]	73	1			T644	7		T540	3		T788	2
values[104]	63	1			T644	8		T540	2		T788	1
values[105]	60	1			T644	7		T540	3		T788	2
values[106]	56	1			T644	5		T540	1		T788	4
values[107]	65	1			T644	8		T540	2		T788	2
values[108]	68	1			T644	4		T540	2		T788	4
values[109]	61	1			T644	5		T540	2		T788	3
values[110]	57	1			T644	4		T540	2		T788	2
values[111]	51	1			T644	4		T540	2		T788	2
values[112]	48	1			T644	2		T540	2		T788	3
values[113]	57	1			T644	1		T540	5		T788	1
values[114]	62	1			T644	3		T540	6		T788	2
values[115]	63	1			T644	3		T540	3		T788	1
values[116]	65	1			T644	5		T540	1		T788	1
values[117]	68	1			T644	5		T788	1		T827	7
values[118]	73	1			T644	4		T788	3		T827	5
values[119]	66	1			T644	5		T788	3		T827	13
values[120]	65	1			T644	3		T788	1		T827	9
values[121]	72	1			T644	4		T788	2		T827	11
values[122]	71	1			T644	4		T788	2		T827	6
values[123]	88	1			T644	3		T788	2		T827	13
values[124]	169	1			T644	4		T788	1		T827	21
values[125]	300	1			T644	10		T788	2		T827	16
values[126]	550	1			T644	16		T788	12		T827	33
values[127]	1853	1			T644	3		T788	84		T827	31
values[128]	3335	1			T644	1		T788	194		T827	2