Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_timer_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	136816	1			T95	3		T96	2		T97	5
values[2]	10667	1			T162	1		T188	1		T189	2
values[3]	4406	1			T458	1		T558	21		T644	68
values[4]	2502	1			T644	22		T476	46		T477	81
values[5]	1652	1			T644	28		T476	16		T477	54
values[6]	1204	1			T644	11		T476	8		T477	30
values[7]	786	1			T644	3		T476	8		T477	28
values[8]	624	1			T476	1		T477	26		T480	17
values[9]	554	1			T477	21		T480	13		T472	2
values[10]	483	1			T477	8		T480	7		T472	7
values[11]	396	1			T477	2		T480	11		T472	14
values[12]	386	1			T480	10		T472	3		T648	5
values[13]	411	1			T480	9		T472	2		T648	8
values[14]	427	1			T480	3		T472	2		T648	9
values[15]	449	1			T480	6		T472	1		T648	14
values[16]	382	1			T480	3		T472	3		T648	5
values[17]	419	1			T480	3		T472	1		T648	10
values[18]	352	1			T480	3		T472	2		T648	3
values[19]	365	1			T480	4		T472	1		T648	6
values[20]	289	1			T480	8		T472	1		T648	5
values[21]	316	1			T480	10		T472	12		T648	11
values[22]	324	1			T480	10		T472	11		T648	14
values[23]	270	1			T480	4		T472	6		T648	2
values[24]	282	1			T480	14		T472	1		T648	5
values[25]	265	1			T480	13		T472	3		T648	3
values[26]	304	1			T480	12		T472	3		T648	4
values[27]	294	1			T480	3		T472	5		T648	6
values[28]	274	1			T480	4		T472	2		T648	3
values[29]	251	1			T480	1		T472	2		T648	5
values[30]	278	1			T480	2		T472	1		T648	10
values[31]	263	1			T480	2		T472	4		T648	5
values[32]	317	1			T480	7		T472	2		T648	19
values[33]	289	1			T480	1		T472	2		T648	8
values[34]	294	1			T480	9		T472	2		T648	9
values[35]	282	1			T480	2		T472	4		T648	5
values[36]	240	1			T480	4		T472	2		T648	10
values[37]	234	1			T480	5		T472	3		T648	7
values[38]	268	1			T480	2		T472	8		T648	3
values[39]	279	1			T480	4		T472	10		T648	10
values[40]	265	1			T480	2		T472	4		T648	6
values[41]	227	1			T480	2		T472	3		T796	1
values[42]	256	1			T480	1		T472	5		T796	1
values[43]	273	1			T480	4		T472	3		T796	1
values[44]	231	1			T480	10		T472	2		T796	1
values[45]	266	1			T480	8		T472	10		T796	1
values[46]	265	1			T480	11		T472	4		T796	1
values[47]	296	1			T480	9		T472	2		T796	1
values[48]	278	1			T480	1		T472	6		T796	1
values[49]	254	1			T480	2		T472	8		T796	1
values[50]	275	1			T480	5		T472	7		T796	1
values[51]	237	1			T480	9		T472	6		T796	1
values[52]	204	1			T480	3		T472	2		T796	1
values[53]	228	1			T480	4		T472	3		T796	1
values[54]	180	1			T480	2		T472	2		T796	1
values[55]	196	1			T480	2		T472	5		T796	1
values[56]	199	1			T480	1		T472	4		T796	1
values[57]	179	1			T480	2		T472	6		T796	1
values[58]	188	1			T480	3		T472	4		T796	1
values[59]	196	1			T480	9		T472	3		T796	1
values[60]	206	1			T480	17		T472	2		T796	1
values[61]	219	1			T480	4		T472	1		T796	1
values[62]	231	1			T480	3		T472	2		T796	1
values[63]	197	1			T480	3		T472	2		T796	1
values[64]	205	1			T480	3		T472	2		T796	1
values[65]	205	1			T480	2		T472	8		T796	1
values[66]	194	1			T480	1		T472	4		T796	1
values[67]	138	1			T480	8		T472	1		T796	1
values[68]	104	1			T472	1		T796	1		T494	2
values[69]	111	1			T472	1		T796	1		T494	1
values[70]	131	1			T472	2		T796	1		T494	1
values[71]	95	1			T472	1		T796	1		T494	3
values[72]	92	1			T472	3		T796	1		T494	1
values[73]	73	1			T472	2		T796	1		T494	3
values[74]	101	1			T472	3		T796	1		T494	3
values[75]	126	1			T472	8		T796	1		T494	10
values[76]	108	1			T472	4		T796	1		T494	7
values[77]	97	1			T472	3		T796	1		T494	6
values[78]	96	1			T472	11		T796	1		T494	1
values[79]	95	1			T472	4		T796	1		T494	1
values[80]	103	1			T472	3		T796	1		T494	5
values[81]	76	1			T472	2		T796	1		T494	3
values[82]	66	1			T472	5		T796	1		T494	1
values[83]	60	1			T472	1		T796	1		T494	6
values[84]	63	1			T472	2		T796	1		T494	3
values[85]	104	1			T472	3		T796	1		T494	6
values[86]	105	1			T472	2		T796	1		T494	6
values[87]	89	1			T472	2		T796	1		T494	1
values[88]	71	1			T472	3		T796	1		T494	3
values[89]	74	1			T472	2		T796	1		T494	1
values[90]	90	1			T472	2		T796	1		T494	1
values[91]	64	1			T472	3		T796	1		T494	2
values[92]	63	1			T472	11		T796	1		T494	2
values[93]	60	1			T472	4		T796	1		T494	4
values[94]	58	1			T472	4		T796	1		T494	5
values[95]	58	1			T472	1		T796	1		T494	7
values[96]	68	1			T472	6		T796	1		T494	10
values[97]	52	1			T472	1		T796	1		T494	4
values[98]	90	1			T472	2		T796	1		T494	5
values[99]	68	1			T472	2		T796	1		T494	5
values[100]	56	1			T472	4		T796	2		T494	3
values[101]	65	1			T472	3		T796	1		T494	3
values[102]	76	1			T472	10		T796	1		T494	2
values[103]	78	1			T472	5		T796	1		T494	1
values[104]	86	1			T472	8		T796	1		T494	3
values[105]	62	1			T472	1		T796	1		T494	5
values[106]	78	1			T472	7		T796	1		T494	5
values[107]	87	1			T472	10		T796	1		T494	4
values[108]	77	1			T472	4		T796	1		T494	5
values[109]	56	1			T472	3		T796	1		T494	4
values[110]	72	1			T472	2		T796	1		T494	5
values[111]	71	1			T472	10		T796	1		T494	3
values[112]	69	1			T472	6		T796	1		T494	5
values[113]	61	1			T472	2		T796	1		T494	3
values[114]	75	1			T472	5		T796	1		T494	9
values[115]	55	1			T472	3		T796	1		T494	2
values[116]	50	1			T472	3		T796	1		T494	2
values[117]	70	1			T472	1		T796	1		T494	6
values[118]	55	1			T796	1		T494	4		T814	3
values[119]	58	1			T796	1		T494	3		T814	7
values[120]	70	1			T796	1		T494	7		T814	3
values[121]	64	1			T796	1		T494	5		T814	9
values[122]	63	1			T796	2		T494	5		T814	11
values[123]	47	1			T796	1		T494	1		T814	9
values[124]	54	1			T796	4		T494	9		T814	5
values[125]	43	1			T796	2		T494	10		T814	4
values[126]	99	1			T796	1		T494	28		T814	18
values[127]	584	1			T796	33		T494	28		T814	65
values[128]	5376	1			T796	377		T494	20		T814	25