Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	134491	1			T95	3		T96	1		T97	3
values[2]	8374	1			T457	5		T458	1		T528	2
values[3]	3261	1			T457	6		T550	1		T793	1
values[4]	1854	1			T457	7		T550	3		T793	1
values[5]	1210	1			T457	6		T550	1		T793	1
values[6]	909	1			T457	11		T550	4		T793	1
values[7]	652	1			T457	10		T550	3		T793	1
values[8]	465	1			T457	12		T550	3		T793	1
values[9]	408	1			T457	3		T550	2		T793	1
values[10]	359	1			T457	6		T550	6		T793	1
values[11]	310	1			T457	9		T550	8		T793	1
values[12]	271	1			T457	5		T550	4		T793	1
values[13]	249	1			T457	5		T550	4		T793	1
values[14]	250	1			T457	5		T550	2		T793	1
values[15]	277	1			T457	10		T550	3		T793	1
values[16]	254	1			T457	6		T550	4		T793	1
values[17]	247	1			T457	6		T550	3		T793	1
values[18]	250	1			T457	8		T550	1		T793	1
values[19]	217	1			T457	7		T550	1		T793	1
values[20]	255	1			T457	6		T550	1		T793	1
values[21]	227	1			T457	3		T550	5		T793	1
values[22]	250	1			T457	5		T550	2		T793	1
values[23]	234	1			T457	11		T550	6		T793	1
values[24]	208	1			T457	9		T550	4		T793	1
values[25]	222	1			T457	3		T550	6		T793	1
values[26]	213	1			T457	7		T550	1		T793	1
values[27]	232	1			T457	4		T550	5		T793	1
values[28]	214	1			T457	3		T550	2		T793	1
values[29]	241	1			T457	2		T550	1		T793	1
values[30]	317	1			T457	12		T550	6		T793	1
values[31]	263	1			T457	19		T550	4		T793	1
values[32]	260	1			T457	5		T550	2		T793	1
values[33]	258	1			T457	7		T550	1		T793	1
values[34]	253	1			T457	6		T550	2		T793	1
values[35]	230	1			T457	11		T550	8		T793	1
values[36]	214	1			T457	12		T550	5		T793	1
values[37]	201	1			T457	3		T550	3		T793	1
values[38]	246	1			T457	6		T550	11		T793	1
values[39]	237	1			T457	7		T550	3		T793	1
values[40]	248	1			T457	8		T550	4		T793	1
values[41]	230	1			T457	2		T550	2		T793	1
values[42]	214	1			T457	3		T550	2		T793	1
values[43]	208	1			T457	5		T550	3		T793	1
values[44]	228	1			T457	8		T550	1		T793	1
values[45]	236	1			T457	11		T550	4		T793	1
values[46]	266	1			T457	4		T550	3		T793	1
values[47]	251	1			T457	7		T550	1		T793	1
values[48]	222	1			T457	6		T550	2		T793	1
values[49]	198	1			T457	10		T550	11		T793	1
values[50]	200	1			T457	7		T550	4		T793	2
values[51]	210	1			T457	5		T550	5		T793	1
values[52]	195	1			T457	5		T550	4		T793	1
values[53]	215	1			T457	3		T550	12		T793	2
values[54]	230	1			T457	4		T550	4		T793	1
values[55]	205	1			T457	16		T550	5		T793	1
values[56]	221	1			T457	9		T550	6		T793	1
values[57]	245	1			T457	11		T550	1		T793	1
values[58]	221	1			T457	8		T550	1		T793	1
values[59]	188	1			T457	14		T550	4		T793	1
values[60]	169	1			T457	9		T550	1		T793	1
values[61]	168	1			T550	3		T793	1		T477	2
values[62]	169	1			T550	1		T793	1		T477	2
values[63]	151	1			T550	4		T793	1		T477	3
values[64]	170	1			T550	5		T793	1		T477	2
values[65]	172	1			T550	3		T793	1		T477	2
values[66]	145	1			T550	1		T793	1		T477	1
values[67]	104	1			T550	3		T793	1		T477	5
values[68]	120	1			T550	1		T793	1		T477	4
values[69]	140	1			T550	4		T793	1		T477	5
values[70]	81	1			T550	3		T793	1		T477	3
values[71]	109	1			T550	1		T793	1		T477	2
values[72]	107	1			T550	2		T793	1		T477	4
values[73]	93	1			T550	2		T793	1		T477	1
values[74]	80	1			T550	2		T793	1		T477	1
values[75]	85	1			T550	2		T793	1		T477	5
values[76]	96	1			T550	1		T793	1		T477	12
values[77]	86	1			T550	3		T793	1		T477	1
values[78]	79	1			T550	5		T793	1		T477	4
values[79]	69	1			T550	5		T793	1		T477	2
values[80]	65	1			T550	2		T793	1		T477	2
values[81]	81	1			T550	3		T793	1		T477	5
values[82]	78	1			T550	4		T793	1		T477	1
values[83]	101	1			T550	6		T793	1		T477	3
values[84]	87	1			T550	3		T793	1		T477	1
values[85]	90	1			T550	10		T793	1		T477	3
values[86]	91	1			T550	4		T793	1		T477	1
values[87]	83	1			T550	3		T793	1		T477	1
values[88]	87	1			T550	2		T793	1		T477	2
values[89]	75	1			T550	2		T793	1		T477	1
values[90]	75	1			T550	5		T793	1		T477	1
values[91]	87	1			T550	5		T793	1		T477	2
values[92]	65	1			T550	3		T793	1		T477	1
values[93]	86	1			T550	2		T793	1		T477	1
values[94]	75	1			T550	2		T793	1		T477	7
values[95]	78	1			T550	5		T793	1		T477	6
values[96]	97	1			T550	3		T793	1		T477	4
values[97]	105	1			T550	5		T793	2		T477	2
values[98]	130	1			T550	7		T793	1		T477	8
values[99]	115	1			T550	6		T793	2		T477	9
values[100]	112	1			T550	6		T793	3		T477	7
values[101]	105	1			T550	2		T793	1		T477	12
values[102]	91	1			T550	2		T793	3		T477	2
values[103]	103	1			T550	4		T793	8		T477	4
values[104]	109	1			T550	2		T793	3		T477	3
values[105]	110	1			T550	4		T793	3		T477	12
values[106]	111	1			T550	7		T793	4		T477	6
values[107]	95	1			T550	1		T793	4		T477	1
values[108]	86	1			T550	4		T793	1		T477	1
values[109]	89	1			T550	4		T793	2		T477	5
values[110]	86	1			T550	1		T793	1		T477	2
values[111]	108	1			T793	3		T477	2		T539	2
values[112]	85	1			T793	3		T477	4		T539	1
values[113]	93	1			T793	1		T477	4		T539	4
values[114]	99	1			T793	1		T477	1		T539	5
values[115]	69	1			T793	2		T477	2		T539	5
values[116]	89	1			T793	1		T477	6		T539	4
values[117]	86	1			T793	1		T477	8		T539	4
values[118]	80	1			T793	2		T477	4		T539	5
values[119]	93	1			T793	3		T477	7		T539	5
values[120]	126	1			T793	6		T477	5		T539	3
values[121]	79	1			T793	2		T477	7		T539	1
values[122]	81	1			T793	3		T477	2		T539	4
values[123]	74	1			T793	1		T477	3		T539	4
values[124]	86	1			T793	1		T477	5		T539	10
values[125]	97	1			T793	2		T477	8		T539	9
values[126]	158	1			T793	9		T477	11		T539	17
values[127]	964	1			T793	26		T477	23		T539	67
values[128]	8226	1			T793	303		T477	8		T539	51