Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	139901	1			T95	7		T96	5		T97	2
values[2]	10580	1			T458	2		T555	2		T528	3
values[3]	3758	1			T558	26		T686	82		T482	1
values[4]	2212	1			T558	8		T686	73		T482	1
values[5]	1428	1			T558	8		T686	54		T482	2
values[6]	1065	1			T558	4		T686	45		T482	6
values[7]	747	1			T558	8		T686	40		T482	3
values[8]	593	1			T558	8		T686	28		T482	8
values[9]	497	1			T558	9		T686	5		T482	4
values[10]	449	1			T558	5		T686	1		T482	8
values[11]	467	1			T482	15		T645	7		T648	6
values[12]	456	1			T482	13		T645	4		T648	10
values[13]	420	1			T482	9		T645	6		T648	5
values[14]	339	1			T482	2		T645	4		T648	10
values[15]	340	1			T482	3		T645	3		T648	18
values[16]	357	1			T482	7		T645	20		T648	6
values[17]	369	1			T482	5		T645	9		T648	3
values[18]	360	1			T482	5		T645	5		T648	2
values[19]	385	1			T482	27		T645	5		T648	6
values[20]	378	1			T482	16		T645	7		T648	8
values[21]	366	1			T482	2		T645	9		T648	19
values[22]	344	1			T482	2		T645	6		T648	9
values[23]	378	1			T482	5		T645	7		T648	4
values[24]	328	1			T482	1		T645	13		T648	3
values[25]	333	1			T482	4		T645	14		T648	5
values[26]	301	1			T482	3		T645	4		T648	9
values[27]	365	1			T482	2		T645	3		T648	4
values[28]	352	1			T482	1		T645	6		T648	9
values[29]	346	1			T482	3		T645	7		T648	10
values[30]	358	1			T482	3		T645	4		T648	12
values[31]	387	1			T482	3		T645	6		T648	3
values[32]	349	1			T482	3		T645	9		T648	18
values[33]	328	1			T482	3		T645	3		T648	5
values[34]	400	1			T482	4		T645	4		T648	4
values[35]	389	1			T482	3		T645	5		T648	11
values[36]	333	1			T482	3		T645	7		T648	2
values[37]	325	1			T482	1		T645	11		T648	6
values[38]	329	1			T482	2		T645	5		T648	3
values[39]	306	1			T482	5		T645	3		T648	5
values[40]	287	1			T482	4		T645	5		T648	3
values[41]	344	1			T482	2		T645	11		T648	12
values[42]	286	1			T482	1		T645	10		T648	5
values[43]	326	1			T482	4		T645	3		T648	25
values[44]	316	1			T482	3		T645	8		T648	8
values[45]	303	1			T482	1		T645	9		T648	4
values[46]	315	1			T482	4		T645	15		T648	13
values[47]	293	1			T482	4		T645	7		T648	3
values[48]	285	1			T482	6		T645	17		T648	9
values[49]	291	1			T482	2		T645	17		T648	6
values[50]	280	1			T482	2		T645	3		T648	2
values[51]	294	1			T482	1		T648	17		T514	6
values[52]	301	1			T482	2		T648	12		T514	3
values[53]	241	1			T482	1		T648	9		T514	5
values[54]	281	1			T482	2		T648	10		T514	13
values[55]	258	1			T482	2		T514	5		T797	6
values[56]	267	1			T482	1		T514	6		T797	11
values[57]	234	1			T482	1		T514	13		T797	9
values[58]	220	1			T482	6		T514	4		T797	3
values[59]	221	1			T482	4		T514	9		T797	3
values[60]	224	1			T482	6		T514	6		T797	3
values[61]	260	1			T482	2		T514	9		T797	3
values[62]	187	1			T482	3		T514	6		T797	6
values[63]	204	1			T482	7		T514	7		T797	1
values[64]	213	1			T482	2		T514	21		T797	2
values[65]	196	1			T482	3		T514	3		T797	4
values[66]	195	1			T482	4		T514	7		T797	2
values[67]	165	1			T482	14		T514	4		T797	3
values[68]	164	1			T482	13		T514	3		T797	6
values[69]	202	1			T482	15		T514	4		T797	11
values[70]	169	1			T482	9		T514	5		T797	18
values[71]	137	1			T482	7		T514	4		T797	11
values[72]	125	1			T482	3		T514	3		T797	13
values[73]	147	1			T482	6		T514	14		T797	16
values[74]	119	1			T482	11		T514	6		T797	5
values[75]	94	1			T482	10		T514	12		T797	5
values[76]	82	1			T482	14		T797	6		T468	10
values[77]	82	1			T482	6		T797	3		T468	18
values[78]	91	1			T482	10		T797	9		T468	8
values[79]	109	1			T482	7		T797	12		T468	21
values[80]	99	1			T482	6		T797	11		T468	9
values[81]	111	1			T482	3		T797	5		T468	12
values[82]	101	1			T482	3		T797	5		T468	4
values[83]	95	1			T482	8		T797	9		T468	8
values[84]	91	1			T482	16		T797	6		T468	5
values[85]	111	1			T482	5		T797	5		T468	14
values[86]	97	1			T482	2		T797	7		T468	15
values[87]	103	1			T482	9		T797	12		T468	15
values[88]	107	1			T482	6		T797	10		T468	11
values[89]	105	1			T482	6		T797	11		T468	7
values[90]	101	1			T482	5		T797	19		T468	4
values[91]	87	1			T482	6		T797	9		T468	5
values[92]	100	1			T482	8		T797	15		T468	8
values[93]	95	1			T482	11		T797	4		T468	9
values[94]	75	1			T482	2		T468	7		T789	2
values[95]	65	1			T482	2		T468	5		T789	2
values[96]	83	1			T468	8		T789	2		T805	1
values[97]	87	1			T468	9		T789	2		T805	1
values[98]	77	1			T468	9		T789	2		T805	1
values[99]	70	1			T468	8		T789	2		T805	1
values[100]	75	1			T468	9		T789	2		T805	1
values[101]	80	1			T468	12		T789	2		T805	1
values[102]	83	1			T468	14		T789	3		T805	1
values[103]	86	1			T468	8		T789	5		T805	1
values[104]	75	1			T468	8		T789	2		T805	1
values[105]	92	1			T468	7		T789	3		T805	1
values[106]	75	1			T468	5		T789	2		T805	1
values[107]	65	1			T468	6		T789	2		T805	1
values[108]	94	1			T468	8		T789	9		T805	1
values[109]	84	1			T468	7		T789	7		T805	1
values[110]	94	1			T468	9		T789	4		T805	1
values[111]	72	1			T468	7		T789	2		T805	1
values[112]	57	1			T468	2		T789	3		T805	2
values[113]	68	1			T468	7		T789	2		T805	1
values[114]	92	1			T468	9		T789	9		T805	1
values[115]	74	1			T468	6		T789	4		T805	2
values[116]	77	1			T468	2		T789	6		T805	1
values[117]	72	1			T468	4		T789	4		T805	2
values[118]	85	1			T468	7		T789	2		T805	5
values[119]	93	1			T468	11		T789	3		T805	1
values[120]	88	1			T468	1		T789	3		T805	2
values[121]	90	1			T789	4		T805	1		T813	3
values[122]	74	1			T789	5		T805	1		T813	1
values[123]	89	1			T789	6		T805	2		T813	8
values[124]	74	1			T789	6		T805	1		T813	9
values[125]	97	1			T789	3		T805	1		T813	12
values[126]	145	1			T789	9		T805	4		T813	5
values[127]	989	1			T789	60		T805	31		T813	16
values[128]	8205	1			T789	589		T805	245		T813	12