Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	135857	1			T95	7		T96	4		T97	3
values[2]	9287	1			T188	1		T551	1		T478	1
values[3]	3393	1			T482	8		T800	23		T644	13
values[4]	1912	1			T482	7		T800	2		T644	3
values[5]	1261	1			T482	3		T476	7		T648	7
values[6]	891	1			T482	2		T476	9		T648	5
values[7]	712	1			T482	1		T476	6		T648	11
values[8]	484	1			T482	3		T476	5		T648	3
values[9]	313	1			T482	5		T476	4		T648	2
values[10]	363	1			T482	8		T476	3		T648	15
values[11]	320	1			T482	1		T476	2		T648	11
values[12]	244	1			T482	1		T476	2		T648	3
values[13]	262	1			T482	2		T476	2		T648	20
values[14]	254	1			T482	3		T476	1		T648	8
values[15]	216	1			T482	3		T476	1		T648	7
values[16]	197	1			T482	1		T476	5		T648	6
values[17]	232	1			T482	1		T476	2		T648	3
values[18]	223	1			T482	9		T476	1		T648	7
values[19]	231	1			T482	10		T476	2		T648	5
values[20]	216	1			T482	9		T476	4		T648	12
values[21]	215	1			T482	1		T476	10		T648	14
values[22]	187	1			T482	1		T476	7		T648	7
values[23]	202	1			T482	4		T476	3		T648	6
values[24]	236	1			T482	1		T476	1		T648	5
values[25]	174	1			T482	5		T476	1		T648	4
values[26]	201	1			T482	6		T476	5		T648	9
values[27]	191	1			T482	1		T476	1		T648	5
values[28]	180	1			T482	1		T476	6		T648	5
values[29]	219	1			T482	6		T476	2		T648	10
values[30]	184	1			T482	1		T476	2		T648	5
values[31]	220	1			T482	5		T476	1		T648	7
values[32]	202	1			T482	5		T476	1		T648	4
values[33]	179	1			T482	6		T476	7		T648	6
values[34]	202	1			T482	1		T476	6		T648	4
values[35]	211	1			T482	1		T476	1		T648	4
values[36]	206	1			T482	3		T476	3		T648	4
values[37]	213	1			T482	5		T476	2		T648	20
values[38]	192	1			T482	1		T476	2		T648	5
values[39]	223	1			T482	5		T476	4		T648	5
values[40]	185	1			T482	4		T476	1		T648	4
values[41]	197	1			T482	1		T648	5		T796	1
values[42]	171	1			T482	3		T648	10		T796	1
values[43]	180	1			T482	1		T648	10		T796	1
values[44]	179	1			T482	1		T648	11		T796	1
values[45]	148	1			T482	2		T648	8		T796	1
values[46]	193	1			T482	2		T648	15		T796	1
values[47]	175	1			T482	1		T648	10		T796	1
values[48]	184	1			T482	2		T648	13		T796	1
values[49]	156	1			T482	3		T648	2		T796	1
values[50]	159	1			T482	1		T648	8		T796	1
values[51]	148	1			T482	3		T648	9		T796	1
values[52]	142	1			T482	9		T648	8		T796	1
values[53]	158	1			T482	2		T648	7		T796	1
values[54]	137	1			T482	3		T648	4		T796	1
values[55]	143	1			T482	3		T648	6		T796	1
values[56]	152	1			T482	2		T648	4		T796	1
values[57]	162	1			T482	4		T648	2		T796	1
values[58]	129	1			T482	2		T796	1		T828	5
values[59]	127	1			T482	4		T796	1		T828	5
values[60]	145	1			T482	3		T796	1		T828	6
values[61]	87	1			T482	2		T796	1		T789	1
values[62]	93	1			T482	2		T796	1		T789	1
values[63]	93	1			T482	1		T796	1		T789	1
values[64]	86	1			T482	5		T796	1		T789	1
values[65]	88	1			T482	2		T796	1		T789	1
values[66]	73	1			T482	3		T796	1		T789	1
values[67]	79	1			T482	3		T796	1		T789	1
values[68]	61	1			T482	2		T796	1		T789	1
values[69]	62	1			T482	1		T796	1		T789	1
values[70]	73	1			T482	4		T796	1		T789	1
values[71]	104	1			T482	3		T796	1		T789	1
values[72]	71	1			T482	5		T796	1		T789	1
values[73]	96	1			T482	8		T796	1		T789	1
values[74]	65	1			T482	7		T796	1		T789	1
values[75]	60	1			T482	7		T796	1		T789	1
values[76]	61	1			T482	8		T796	1		T789	1
values[77]	55	1			T482	5		T796	1		T789	1
values[78]	72	1			T482	9		T796	1		T789	1
values[79]	75	1			T482	8		T796	1		T789	1
values[80]	64	1			T482	5		T796	1		T789	1
values[81]	67	1			T482	3		T796	1		T789	1
values[82]	62	1			T482	9		T796	1		T789	1
values[83]	66	1			T482	6		T796	1		T789	2
values[84]	49	1			T482	4		T796	1		T789	1
values[85]	57	1			T482	3		T796	1		T789	1
values[86]	65	1			T482	2		T796	1		T789	1
values[87]	61	1			T482	7		T796	1		T789	1
values[88]	73	1			T482	7		T796	1		T789	1
values[89]	79	1			T482	10		T796	1		T789	1
values[90]	57	1			T482	4		T796	1		T789	1
values[91]	55	1			T482	10		T796	1		T789	1
values[92]	56	1			T482	1		T796	1		T789	1
values[93]	58	1			T482	5		T796	1		T789	1
values[94]	74	1			T482	8		T796	1		T789	1
values[95]	46	1			T482	3		T796	1		T789	1
values[96]	63	1			T482	7		T796	1		T789	1
values[97]	54	1			T482	3		T796	1		T789	1
values[98]	53	1			T482	4		T796	1		T789	1
values[99]	64	1			T482	10		T796	1		T789	1
values[100]	60	1			T482	3		T796	1		T789	1
values[101]	56	1			T482	3		T796	1		T789	1
values[102]	57	1			T482	2		T796	1		T789	1
values[103]	58	1			T482	1		T796	1		T789	1
values[104]	60	1			T482	3		T796	1		T789	1
values[105]	84	1			T482	9		T796	1		T789	1
values[106]	63	1			T482	5		T796	1		T789	1
values[107]	62	1			T482	10		T796	1		T789	1
values[108]	69	1			T482	2		T796	1		T789	1
values[109]	70	1			T482	4		T796	1		T789	1
values[110]	54	1			T482	3		T796	1		T789	1
values[111]	51	1			T482	6		T796	3		T789	1
values[112]	59	1			T482	3		T796	6		T789	1
values[113]	58	1			T482	3		T796	4		T789	1
values[114]	56	1			T482	2		T796	1		T789	1
values[115]	62	1			T482	2		T796	1		T789	1
values[116]	67	1			T482	4		T796	1		T789	1
values[117]	47	1			T482	3		T796	1		T789	1
values[118]	59	1			T482	1		T796	1		T789	1
values[119]	63	1			T482	3		T796	3		T789	1
values[120]	63	1			T482	2		T796	9		T789	1
values[121]	51	1			T482	1		T796	2		T789	1
values[122]	71	1			T482	3		T796	1		T789	1
values[123]	56	1			T482	2		T796	1		T789	1
values[124]	67	1			T482	5		T796	2		T789	1
values[125]	91	1			T482	7		T796	5		T789	1
values[126]	160	1			T482	5		T796	2		T789	3
values[127]	846	1			T482	10		T796	37		T789	24
values[128]	6953	1			T482	4		T796	340		T789	304