Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	130678	1			T95	3		T96	3		T97	4
values[2]	9072	1			T162	2		T188	1		T189	1
values[3]	3772	1			T550	4		T644	51		T839	1
values[4]	2304	1			T550	3		T644	59		T477	71
values[5]	1575	1			T550	5		T644	68		T477	33
values[6]	1269	1			T550	5		T644	46		T477	17
values[7]	922	1			T550	4		T644	26		T477	12
values[8]	685	1			T550	7		T644	34		T477	14
values[9]	555	1			T550	9		T644	29		T477	22
values[10]	477	1			T550	3		T644	18		T477	25
values[11]	378	1			T550	5		T644	6		T477	22
values[12]	362	1			T550	8		T477	21		T542	1
values[13]	304	1			T550	9		T477	3		T542	1
values[14]	273	1			T550	8		T542	2		T622	6
values[15]	238	1			T550	6		T542	5		T622	1
values[16]	281	1			T550	9		T542	1		T622	1
values[17]	272	1			T550	7		T542	2		T622	2
values[18]	293	1			T550	5		T542	1		T622	1
values[19]	267	1			T550	4		T542	1		T622	4
values[20]	286	1			T550	3		T542	3		T622	1
values[21]	259	1			T550	9		T542	3		T622	2
values[22]	252	1			T550	10		T542	2		T622	1
values[23]	256	1			T550	7		T542	2		T622	5
values[24]	262	1			T550	4		T542	3		T622	6
values[25]	254	1			T550	4		T542	3		T622	2
values[26]	243	1			T550	6		T542	8		T622	3
values[27]	197	1			T550	2		T542	2		T541	5
values[28]	218	1			T550	6		T542	1		T541	7
values[29]	251	1			T550	8		T542	2		T541	14
values[30]	275	1			T550	15		T542	1		T541	18
values[31]	244	1			T550	13		T542	2		T541	11
values[32]	243	1			T550	10		T542	3		T541	3
values[33]	231	1			T550	3		T542	1		T541	8
values[34]	211	1			T550	2		T542	2		T541	15
values[35]	224	1			T550	5		T542	1		T541	14
values[36]	252	1			T550	5		T542	2		T541	10
values[37]	246	1			T550	5		T542	3		T541	3
values[38]	240	1			T550	7		T542	5		T541	5
values[39]	202	1			T550	7		T542	3		T541	5
values[40]	210	1			T550	10		T542	3		T541	5
values[41]	184	1			T550	10		T542	2		T541	11
values[42]	220	1			T550	6		T542	4		T541	7
values[43]	227	1			T550	17		T542	1		T541	4
values[44]	216	1			T550	10		T542	4		T541	5
values[45]	208	1			T550	8		T542	3		T541	5
values[46]	209	1			T550	2		T542	5		T541	6
values[47]	215	1			T550	4		T542	2		T541	5
values[48]	221	1			T550	7		T542	3		T541	10
values[49]	224	1			T550	10		T542	5		T541	8
values[50]	185	1			T550	3		T542	4		T541	12
values[51]	192	1			T550	7		T542	6		T541	6
values[52]	189	1			T550	10		T542	4		T541	14
values[53]	163	1			T550	10		T542	5		T541	4
values[54]	194	1			T550	5		T542	3		T541	18
values[55]	182	1			T550	9		T542	2		T541	12
values[56]	216	1			T550	4		T542	1		T541	13
values[57]	188	1			T550	5		T542	3		T541	3
values[58]	175	1			T550	4		T542	2		T541	2
values[59]	173	1			T550	3		T542	2		T541	2
values[60]	143	1			T550	3		T542	2		T840	3
values[61]	137	1			T550	8		T542	1		T840	3
values[62]	140	1			T550	3		T542	1		T840	5
values[63]	170	1			T550	4		T542	5		T840	17
values[64]	164	1			T550	6		T542	3		T840	6
values[65]	140	1			T550	3		T542	1		T840	2
values[66]	124	1			T550	2		T542	1		T788	1
values[67]	162	1			T550	5		T542	1		T788	1
values[68]	122	1			T550	5		T542	5		T788	1
values[69]	144	1			T550	7		T542	5		T788	1
values[70]	127	1			T550	4		T542	6		T788	1
values[71]	122	1			T550	5		T542	4		T788	1
values[72]	119	1			T550	4		T542	3		T788	1
values[73]	112	1			T550	6		T542	6		T788	1
values[74]	116	1			T550	7		T542	3		T788	1
values[75]	100	1			T550	5		T542	3		T788	1
values[76]	106	1			T550	4		T542	3		T788	1
values[77]	105	1			T550	14		T542	1		T788	1
values[78]	110	1			T550	15		T542	2		T788	1
values[79]	68	1			T550	7		T542	2		T788	1
values[80]	58	1			T550	9		T542	3		T788	1
values[81]	74	1			T550	7		T542	3		T788	1
values[82]	65	1			T550	10		T542	1		T788	1
values[83]	67	1			T550	7		T542	1		T788	1
values[84]	58	1			T550	8		T542	1		T788	1
values[85]	70	1			T550	19		T542	4		T788	1
values[86]	66	1			T550	20		T542	1		T788	1
values[87]	79	1			T550	18		T542	3		T788	1
values[88]	63	1			T550	7		T542	2		T788	1
values[89]	72	1			T550	6		T542	3		T788	1
values[90]	66	1			T550	7		T542	1		T788	1
values[91]	61	1			T550	6		T542	3		T788	1
values[92]	72	1			T550	5		T542	3		T788	1
values[93]	81	1			T550	11		T542	6		T788	1
values[94]	83	1			T550	10		T542	4		T788	1
values[95]	68	1			T550	10		T542	1		T788	2
values[96]	77	1			T550	14		T542	2		T788	1
values[97]	78	1			T550	9		T542	2		T788	1
values[98]	61	1			T550	9		T542	2		T788	1
values[99]	73	1			T550	13		T542	2		T788	1
values[100]	81	1			T550	9		T542	2		T788	1
values[101]	79	1			T550	7		T542	6		T788	1
values[102]	84	1			T550	3		T542	3		T788	1
values[103]	99	1			T550	10		T542	4		T788	1
values[104]	93	1			T550	9		T542	2		T788	1
values[105]	87	1			T550	3		T542	2		T788	1
values[106]	83	1			T550	4		T542	5		T788	1
values[107]	67	1			T550	6		T542	5		T788	1
values[108]	77	1			T550	12		T542	7		T788	1
values[109]	69	1			T550	6		T542	2		T788	1
values[110]	70	1			T550	5		T542	2		T788	1
values[111]	85	1			T550	6		T542	2		T788	1
values[112]	69	1			T550	5		T542	2		T788	1
values[113]	60	1			T550	7		T542	4		T788	1
values[114]	62	1			T550	8		T542	2		T788	2
values[115]	71	1			T550	8		T542	3		T788	1
values[116]	56	1			T550	4		T542	3		T788	3
values[117]	69	1			T550	5		T542	6		T788	4
values[118]	81	1			T550	7		T542	7		T788	1
values[119]	70	1			T550	9		T542	4		T788	7
values[120]	67	1			T550	9		T542	2		T788	1
values[121]	71	1			T550	9		T542	3		T788	1
values[122]	67	1			T550	15		T542	2		T788	1
values[123]	48	1			T550	1		T542	3		T788	1
values[124]	69	1			T550	2		T542	2		T788	3
values[125]	72	1			T550	5		T542	3		T788	1
values[126]	174	1			T550	28		T542	18		T788	3
values[127]	1096	1			T550	63		T542	58		T788	27
values[128]	8339	1			T550	30		T542	21		T788	352