Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	134957	1			T95	2		T96	4		T97	3
values[2]	10999	1			T456	1		T478	3		T568	1
values[3]	4620	1			T478	1		T550	104		T558	36
values[4]	2734	1			T550	42		T558	15		T686	79
values[5]	1754	1			T550	12		T558	10		T686	53
values[6]	1247	1			T550	2		T558	10		T686	47
values[7]	873	1			T558	5		T686	43		T482	32
values[8]	591	1			T558	4		T686	26		T482	3
values[9]	462	1			T558	10		T686	8		T482	1
values[10]	378	1			T558	12		T686	6		T824	1
values[11]	353	1			T824	1		T648	12		T514	2
values[12]	331	1			T824	1		T648	18		T514	7
values[13]	284	1			T824	1		T648	7		T514	12
values[14]	244	1			T824	1		T648	27		T514	7
values[15]	278	1			T824	1		T648	13		T514	9
values[16]	356	1			T824	1		T648	25		T514	4
values[17]	276	1			T824	1		T648	22		T514	5
values[18]	298	1			T824	1		T648	13		T514	5
values[19]	264	1			T824	1		T648	13		T514	4
values[20]	271	1			T824	1		T648	9		T514	6
values[21]	313	1			T824	1		T648	14		T514	17
values[22]	297	1			T824	1		T648	9		T514	10
values[23]	266	1			T824	1		T648	19		T514	4
values[24]	258	1			T824	1		T648	23		T514	4
values[25]	292	1			T824	1		T648	20		T514	6
values[26]	271	1			T824	1		T648	16		T514	7
values[27]	277	1			T824	1		T648	23		T514	5
values[28]	265	1			T824	1		T648	14		T514	10
values[29]	289	1			T824	1		T648	12		T514	7
values[30]	288	1			T824	1		T648	8		T514	6
values[31]	284	1			T824	1		T648	8		T514	5
values[32]	303	1			T824	1		T648	11		T514	7
values[33]	242	1			T824	1		T648	13		T514	2
values[34]	275	1			T824	1		T648	13		T514	7
values[35]	275	1			T824	1		T648	15		T514	15
values[36]	220	1			T824	1		T648	14		T514	6
values[37]	278	1			T824	1		T648	13		T514	21
values[38]	246	1			T824	1		T648	9		T514	5
values[39]	283	1			T824	1		T648	18		T514	3
values[40]	273	1			T824	1		T648	19		T514	4
values[41]	274	1			T824	1		T648	20		T514	8
values[42]	288	1			T824	1		T648	29		T514	6
values[43]	295	1			T824	1		T648	15		T514	7
values[44]	242	1			T824	1		T648	20		T514	24
values[45]	240	1			T824	1		T648	29		T514	11
values[46]	236	1			T824	1		T648	13		T514	7
values[47]	227	1			T824	1		T648	12		T514	5
values[48]	217	1			T824	1		T648	12		T514	4
values[49]	201	1			T824	1		T648	14		T514	3
values[50]	206	1			T824	1		T648	13		T514	5
values[51]	238	1			T824	1		T648	12		T514	15
values[52]	245	1			T824	2		T648	12		T514	6
values[53]	205	1			T824	1		T648	8		T514	6
values[54]	287	1			T824	1		T648	14		T514	15
values[55]	199	1			T824	1		T648	6		T514	14
values[56]	270	1			T824	2		T648	19		T514	3
values[57]	196	1			T824	1		T648	11		T514	5
values[58]	195	1			T824	1		T648	8		T514	11
values[59]	194	1			T824	1		T648	14		T514	4
values[60]	200	1			T824	1		T648	9		T514	13
values[61]	192	1			T824	1		T648	37		T514	7
values[62]	150	1			T824	1		T648	16		T514	7
values[63]	149	1			T824	1		T648	16		T514	6
values[64]	107	1			T824	1		T648	6		T796	1
values[65]	99	1			T824	1		T648	3		T796	1
values[66]	112	1			T824	1		T648	4		T796	1
values[67]	120	1			T824	1		T648	5		T796	1
values[68]	103	1			T824	1		T648	8		T796	1
values[69]	97	1			T824	1		T796	1		T812	3
values[70]	83	1			T824	1		T796	1		T812	4
values[71]	80	1			T824	1		T796	1		T812	4
values[72]	70	1			T824	1		T796	1		T812	11
values[73]	75	1			T824	1		T796	1		T812	16
values[74]	99	1			T824	1		T796	1		T812	14
values[75]	99	1			T824	1		T796	1		T812	10
values[76]	96	1			T824	1		T796	1		T812	16
values[77]	109	1			T824	1		T796	1		T812	36
values[78]	91	1			T824	1		T796	1		T812	34
values[79]	94	1			T824	1		T796	1		T812	25
values[80]	74	1			T824	1		T796	1		T812	9
values[81]	73	1			T824	1		T796	1		T812	14
values[82]	49	1			T824	1		T796	1		T812	4
values[83]	48	1			T824	1		T796	1		T812	3
values[84]	53	1			T824	1		T796	1		T494	5
values[85]	48	1			T824	1		T796	1		T494	5
values[86]	55	1			T824	1		T796	1		T494	12
values[87]	55	1			T824	1		T796	1		T494	12
values[88]	55	1			T824	1		T796	1		T494	13
values[89]	44	1			T824	1		T796	1		T494	7
values[90]	62	1			T824	1		T796	1		T494	18
values[91]	56	1			T824	1		T796	1		T494	13
values[92]	44	1			T824	1		T796	1		T494	10
values[93]	50	1			T824	1		T796	1		T494	7
values[94]	43	1			T824	1		T796	1		T494	2
values[95]	45	1			T824	1		T796	1		T494	6
values[96]	47	1			T824	1		T796	1		T494	3
values[97]	46	1			T824	1		T796	1		T494	5
values[98]	65	1			T824	7		T796	1		T494	10
values[99]	46	1			T824	1		T796	1		T494	4
values[100]	51	1			T824	3		T796	1		T494	7
values[101]	49	1			T824	1		T796	1		T494	6
values[102]	63	1			T824	1		T796	2		T494	7
values[103]	51	1			T824	3		T796	1		T494	9
values[104]	58	1			T824	2		T796	1		T494	15
values[105]	49	1			T824	2		T796	1		T494	7
values[106]	64	1			T824	2		T796	1		T494	8
values[107]	53	1			T824	2		T796	1		T494	7
values[108]	70	1			T824	3		T796	1		T494	18
values[109]	59	1			T824	8		T796	1		T494	11
values[110]	73	1			T824	1		T796	1		T494	17
values[111]	67	1			T824	3		T796	1		T494	4
values[112]	66	1			T824	2		T796	1		T494	14
values[113]	65	1			T824	1		T796	1		T494	13
values[114]	64	1			T824	1		T796	1		T494	8
values[115]	48	1			T824	1		T796	1		T494	6
values[116]	51	1			T824	1		T796	1		T494	5
values[117]	50	1			T824	1		T796	1		T494	3
values[118]	58	1			T824	3		T796	1		T494	6
values[119]	57	1			T824	2		T796	1		T494	9
values[120]	61	1			T824	1		T796	6		T494	8
values[121]	58	1			T824	2		T796	1		T494	9
values[122]	63	1			T824	2		T796	1		T494	9
values[123]	56	1			T824	4		T796	1		T494	8
values[124]	72	1			T824	1		T796	1		T494	21
values[125]	74	1			T824	2		T796	7		T494	21
values[126]	116	1			T824	2		T796	2		T494	40
values[127]	895	1			T824	37		T796	30		T494	73
values[128]	8115	1			T824	357		T796	247		T494	19