Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	134599	1			T95	6		T96	1		T97	3
values[2]	7735	1			T559	1		T460	1		T458	4
values[3]	3320	1			T841	6		T540	6		T472	50
values[4]	2106	1			T841	8		T472	52		T648	19
values[5]	1314	1			T841	16		T472	63		T648	10
values[6]	1061	1			T841	8		T472	61		T648	8
values[7]	764	1			T841	5		T472	13		T648	13
values[8]	696	1			T841	16		T472	1		T648	17
values[9]	597	1			T841	9		T648	6		T514	8
values[10]	529	1			T841	5		T648	3		T514	6
values[11]	510	1			T841	9		T648	10		T514	5
values[12]	570	1			T841	5		T648	6		T514	18
values[13]	554	1			T841	6		T648	10		T514	14
values[14]	511	1			T841	12		T648	13		T514	16
values[15]	454	1			T841	15		T648	7		T514	6
values[16]	455	1			T841	11		T648	9		T514	4
values[17]	465	1			T841	10		T648	19		T514	9
values[18]	505	1			T841	3		T648	6		T514	23
values[19]	500	1			T841	11		T648	6		T514	7
values[20]	409	1			T841	8		T648	18		T514	8
values[21]	425	1			T841	21		T648	11		T514	13
values[22]	453	1			T841	5		T648	7		T514	9
values[23]	578	1			T841	11		T648	22		T514	9
values[24]	481	1			T841	14		T648	8		T514	8
values[25]	413	1			T841	6		T648	9		T514	13
values[26]	488	1			T841	8		T648	25		T514	7
values[27]	443	1			T841	8		T648	11		T514	5
values[28]	413	1			T841	8		T648	10		T514	6
values[29]	360	1			T841	16		T648	4		T514	4
values[30]	390	1			T841	18		T648	5		T514	10
values[31]	407	1			T841	7		T648	3		T514	11
values[32]	451	1			T841	24		T648	12		T514	11
values[33]	495	1			T841	16		T648	18		T514	16
values[34]	480	1			T841	13		T648	23		T514	17
values[35]	429	1			T841	21		T648	8		T514	10
values[36]	346	1			T841	4		T648	4		T514	9
values[37]	399	1			T841	12		T648	9		T514	13
values[38]	325	1			T841	2		T648	4		T514	6
values[39]	315	1			T648	5		T514	15		T796	1
values[40]	367	1			T648	15		T514	30		T796	1
values[41]	351	1			T648	10		T514	5		T796	1
values[42]	364	1			T648	7		T514	10		T796	1
values[43]	267	1			T648	12		T514	6		T796	1
values[44]	269	1			T648	7		T514	5		T796	1
values[45]	317	1			T648	11		T514	8		T796	1
values[46]	279	1			T648	6		T514	5		T796	1
values[47]	268	1			T648	43		T514	8		T796	1
values[48]	294	1			T648	9		T514	5		T796	1
values[49]	203	1			T648	9		T514	8		T796	1
values[50]	203	1			T648	8		T514	17		T796	1
values[51]	192	1			T514	4		T796	1		T541	3
values[52]	149	1			T514	10		T796	1		T541	11
values[53]	152	1			T514	9		T796	1		T541	8
values[54]	133	1			T514	8		T796	2		T789	1
values[55]	83	1			T514	5		T796	1		T789	1
values[56]	75	1			T514	6		T796	1		T789	1
values[57]	68	1			T796	1		T789	1		T805	1
values[58]	91	1			T796	1		T789	1		T805	1
values[59]	69	1			T796	1		T789	1		T805	1
values[60]	71	1			T796	1		T789	1		T805	1
values[61]	84	1			T796	1		T789	1		T805	1
values[62]	69	1			T796	1		T789	1		T805	1
values[63]	78	1			T796	1		T789	1		T805	1
values[64]	127	1			T796	1		T789	1		T805	1
values[65]	126	1			T796	1		T789	1		T805	1
values[66]	114	1			T796	1		T789	1		T805	1
values[67]	122	1			T796	1		T789	1		T805	1
values[68]	114	1			T796	1		T789	1		T805	1
values[69]	85	1			T796	1		T789	1		T805	1
values[70]	114	1			T796	1		T789	1		T805	1
values[71]	110	1			T796	1		T789	1		T805	1
values[72]	74	1			T796	1		T789	1		T805	2
values[73]	65	1			T796	1		T789	2		T805	1
values[74]	78	1			T796	1		T789	1		T805	1
values[75]	56	1			T796	1		T789	1		T805	1
values[76]	61	1			T796	1		T789	1		T805	1
values[77]	66	1			T796	1		T789	1		T805	1
values[78]	62	1			T796	1		T789	1		T805	1
values[79]	74	1			T796	1		T789	1		T805	1
values[80]	49	1			T796	1		T789	1		T805	1
values[81]	64	1			T796	1		T789	1		T805	1
values[82]	55	1			T796	1		T789	1		T805	1
values[83]	56	1			T796	1		T789	1		T805	1
values[84]	93	1			T796	1		T789	1		T805	1
values[85]	106	1			T796	1		T789	1		T805	1
values[86]	84	1			T796	1		T789	1		T805	1
values[87]	54	1			T796	1		T789	1		T805	2
values[88]	83	1			T796	1		T789	1		T805	1
values[89]	80	1			T796	1		T789	1		T805	1
values[90]	69	1			T796	1		T789	1		T805	1
values[91]	50	1			T796	1		T789	1		T805	1
values[92]	67	1			T796	1		T789	1		T805	1
values[93]	73	1			T796	1		T789	1		T805	1
values[94]	52	1			T796	1		T789	1		T805	1
values[95]	50	1			T796	1		T789	1		T805	1
values[96]	54	1			T796	1		T789	1		T805	1
values[97]	46	1			T796	1		T789	1		T805	1
values[98]	54	1			T796	1		T789	1		T805	1
values[99]	31	1			T796	1		T789	1		T805	1
values[100]	53	1			T796	1		T789	1		T805	1
values[101]	51	1			T796	1		T789	1		T805	1
values[102]	47	1			T796	1		T789	1		T805	1
values[103]	37	1			T796	1		T789	1		T805	1
values[104]	33	1			T796	1		T789	1		T805	1
values[105]	37	1			T796	1		T789	1		T805	1
values[106]	37	1			T796	2		T789	1		T805	1
values[107]	44	1			T796	5		T789	1		T805	1
values[108]	36	1			T796	2		T789	1		T805	1
values[109]	37	1			T796	1		T789	1		T805	1
values[110]	41	1			T796	2		T789	9		T805	1
values[111]	31	1			T796	1		T789	3		T805	1
values[112]	45	1			T796	2		T789	5		T805	1
values[113]	38	1			T796	1		T789	2		T805	1
values[114]	38	1			T796	2		T789	1		T805	5
values[115]	40	1			T796	1		T789	2		T805	1
values[116]	32	1			T796	1		T789	2		T805	1
values[117]	42	1			T796	3		T789	2		T805	2
values[118]	36	1			T796	1		T789	4		T805	2
values[119]	37	1			T796	1		T789	2		T805	1
values[120]	41	1			T796	2		T789	4		T805	4
values[121]	44	1			T796	1		T789	4		T805	4
values[122]	48	1			T796	4		T789	1		T805	3
values[123]	43	1			T796	2		T789	1		T805	5
values[124]	40	1			T796	1		T789	2		T805	1
values[125]	34	1			T796	2		T789	1		T805	2
values[126]	88	1			T796	3		T789	4		T805	7
values[127]	1159	1			T796	76		T789	60		T805	71
values[128]	5600	1			T796	315		T789	267		T805	355