Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	145981	1			T95	5		T96	1		T97	4
values[2]	4715	1			T458	3		T555	2		T554	2
values[3]	2427	1			T576	1		T482	89		T644	2
values[4]	1826	1			T482	75		T644	1		T476	2
values[5]	1358	1			T482	70		T644	1		T476	1
values[6]	1151	1			T482	37		T644	3		T476	3
values[7]	976	1			T482	37		T644	2		T476	3
values[8]	955	1			T482	20		T644	2		T476	1
values[9]	739	1			T482	7		T644	4		T476	1
values[10]	652	1			T644	1		T476	2		T480	25
values[11]	624	1			T644	2		T476	2		T480	13
values[12]	551	1			T644	3		T476	2		T480	8
values[13]	479	1			T644	2		T476	3		T480	12
values[14]	504	1			T644	5		T476	5		T480	3
values[15]	435	1			T644	1		T476	1		T480	3
values[16]	444	1			T644	1		T476	2		T480	3
values[17]	398	1			T644	3		T476	1		T480	2
values[18]	414	1			T644	1		T476	1		T480	5
values[19]	403	1			T644	4		T476	1		T480	2
values[20]	354	1			T644	5		T476	1		T480	2
values[21]	300	1			T644	4		T476	1		T480	4
values[22]	280	1			T644	4		T476	10		T480	3
values[23]	297	1			T644	4		T476	5		T480	2
values[24]	276	1			T644	3		T476	3		T480	1
values[25]	309	1			T644	1		T476	2		T480	2
values[26]	277	1			T644	4		T476	3		T480	1
values[27]	223	1			T644	2		T476	2		T480	4
values[28]	182	1			T644	2		T476	5		T480	1
values[29]	169	1			T644	1		T476	4		T480	1
values[30]	206	1			T644	2		T476	3		T480	5
values[31]	193	1			T644	2		T476	1		T480	10
values[32]	127	1			T644	1		T476	1		T480	2
values[33]	144	1			T644	3		T476	2		T480	4
values[34]	160	1			T644	4		T476	1		T480	6
values[35]	180	1			T644	4		T476	3		T480	2
values[36]	177	1			T644	3		T476	2		T480	2
values[37]	131	1			T644	4		T476	1		T480	2
values[38]	112	1			T644	3		T476	2		T480	4
values[39]	110	1			T644	2		T476	3		T480	4
values[40]	85	1			T644	2		T476	2		T480	4
values[41]	102	1			T644	1		T476	3		T480	3
values[42]	95	1			T644	3		T476	6		T480	3
values[43]	91	1			T644	1		T476	3		T480	1
values[44]	104	1			T644	2		T476	2		T480	6
values[45]	103	1			T644	3		T476	3		T480	1
values[46]	109	1			T644	3		T476	2		T480	3
values[47]	96	1			T644	4		T476	4		T480	3
values[48]	86	1			T644	6		T476	3		T480	2
values[49]	78	1			T644	1		T476	1		T480	1
values[50]	64	1			T644	2		T476	1		T480	5
values[51]	66	1			T644	3		T476	2		T480	6
values[52]	75	1			T644	6		T476	7		T480	1
values[53]	70	1			T644	1		T476	7		T480	3
values[54]	63	1			T644	3		T476	6		T480	2
values[55]	73	1			T644	7		T476	4		T480	5
values[56]	72	1			T644	5		T476	1		T480	5
values[57]	78	1			T644	2		T476	2		T480	6
values[58]	69	1			T644	4		T476	2		T480	6
values[59]	82	1			T644	1		T476	4		T480	6
values[60]	68	1			T644	1		T476	3		T480	2
values[61]	68	1			T644	7		T476	2		T480	5
values[62]	58	1			T644	4		T476	2		T480	7
values[63]	70	1			T644	1		T476	2		T480	6
values[64]	71	1			T644	6		T476	3		T480	8
values[65]	55	1			T644	5		T476	1		T480	3
values[66]	52	1			T644	1		T476	1		T480	1
values[67]	56	1			T644	1		T476	2		T480	2
values[68]	60	1			T644	2		T476	1		T480	3
values[69]	63	1			T644	2		T476	1		T480	1
values[70]	65	1			T644	3		T476	2		T480	2
values[71]	63	1			T644	2		T476	5		T480	6
values[72]	63	1			T644	5		T476	3		T480	2
values[73]	75	1			T644	1		T476	3		T480	6
values[74]	71	1			T644	3		T476	3		T480	2
values[75]	69	1			T644	1		T476	2		T480	3
values[76]	51	1			T644	1		T476	1		T480	1
values[77]	68	1			T644	3		T476	3		T480	6
values[78]	69	1			T644	1		T476	6		T480	6
values[79]	64	1			T644	1		T476	6		T480	3
values[80]	64	1			T644	2		T476	3		T480	1
values[81]	51	1			T644	2		T476	1		T480	2
values[82]	73	1			T644	3		T476	1		T480	2
values[83]	79	1			T644	5		T476	1		T480	6
values[84]	69	1			T644	1		T476	4		T480	1
values[85]	73	1			T644	2		T476	3		T480	3
values[86]	78	1			T644	3		T476	1		T480	4
values[87]	59	1			T644	1		T476	3		T480	1
values[88]	66	1			T644	3		T476	2		T480	3
values[89]	63	1			T644	1		T476	2		T480	1
values[90]	75	1			T644	2		T476	2		T480	4
values[91]	92	1			T644	3		T476	8		T480	2
values[92]	89	1			T644	2		T476	9		T480	1
values[93]	73	1			T644	1		T476	1		T480	4
values[94]	82	1			T644	2		T476	2		T480	5
values[95]	81	1			T644	3		T476	4		T480	3
values[96]	94	1			T644	3		T476	8		T480	1
values[97]	107	1			T644	7		T476	7		T480	1
values[98]	97	1			T644	8		T476	4		T480	4
values[99]	78	1			T644	4		T476	3		T480	2
values[100]	98	1			T644	7		T476	5		T480	1
values[101]	77	1			T644	4		T476	4		T480	5
values[102]	100	1			T644	9		T476	4		T480	6
values[103]	85	1			T644	1		T476	2		T480	9
values[104]	78	1			T644	4		T476	2		T480	7
values[105]	86	1			T644	6		T476	2		T480	4
values[106]	77	1			T644	4		T476	2		T480	3
values[107]	90	1			T644	1		T476	1		T480	3
values[108]	93	1			T644	1		T476	4		T480	2
values[109]	97	1			T644	7		T476	6		T480	7
values[110]	115	1			T644	5		T476	4		T480	6
values[111]	96	1			T644	1		T476	1		T480	9
values[112]	83	1			T644	3		T476	2		T480	2
values[113]	101	1			T644	3		T476	5		T480	4
values[114]	88	1			T644	3		T476	6		T480	7
values[115]	84	1			T644	4		T476	5		T480	3
values[116]	89	1			T644	5		T476	2		T480	2
values[117]	100	1			T644	6		T476	2		T480	4
values[118]	130	1			T644	6		T476	4		T480	6
values[119]	118	1			T644	5		T476	6		T480	5
values[120]	110	1			T644	6		T476	5		T480	6
values[121]	108	1			T644	3		T476	4		T480	12
values[122]	123	1			T644	5		T476	6		T480	3
values[123]	145	1			T644	4		T476	11		T480	2
values[124]	244	1			T644	8		T476	23		T480	12
values[125]	506	1			T644	43		T476	54		T480	30
values[126]	1047	1			T644	43		T476	65		T480	31
values[127]	3532	1			T644	22		T476	34		T480	8
values[128]	6190	1			T644	2		T476	4		T480	1