Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	418	1			T568	1		T550	1		T558	1
all_values[1]	408	1			T560	4		T644	1		T476	3
all_values[2]	442	1			T558	1		T874	1		T560	1
all_values[3]	437	1			T550	1		T686	1		T874	1
all_values[4]	428	1			T457	1		T568	1		T686	1
all_values[5]	421	1			T457	1		T560	5		T645	3
all_values[6]	431	1			T568	1		T560	3		T794	1
all_values[7]	415	1			T686	1		T874	1		T560	4
all_values[8]	406	1			T686	1		T560	2		T800	1
all_values[9]	448	1			T568	1		T686	1		T560	3
all_values[10]	473	1			T558	1		T874	1		T560	2
all_values[11]	475	1			T560	4		T433	1		T482	1
all_values[12]	437	1			T457	1		T568	1		T550	1
all_values[13]	414	1			T874	1		T560	1		T794	1
all_values[14]	454	1			T568	1		T686	1		T874	1
all_values[15]	463	1			T457	1		T560	4		T482	1
all_values[16]	404	1			T550	1		T560	1		T482	1
all_values[17]	415	1			T568	1		T550	1		T558	1
all_values[18]	436	1			T560	3		T794	2		T644	1
all_values[19]	423	1			T560	3		T433	1		T644	1
all_values[20]	439	1			T568	2		T558	2		T560	5
all_values[21]	512	1			T568	1		T686	1		T560	4
all_values[22]	421	1			T874	1		T560	3		T794	1
all_values[23]	440	1			T560	3		T482	1		T800	1
all_values[24]	401	1			T550	2		T794	1		T644	1
all_values[25]	421	1			T550	1		T558	2		T686	1
all_values[26]	414	1			T457	1		T550	1		T560	3
all_values[27]	435	1			T560	3		T794	1		T645	3
all_values[28]	440	1			T457	1		T550	1		T558	2
all_values[29]	410	1			T550	1		T558	1		T874	2
all_values[30]	458	1			T558	1		T560	2		T794	3
all_values[31]	461	1			T457	1		T550	1		T874	1
all_values[32]	448	1			T550	2		T558	1		T560	1
all_values[33]	424	1			T550	1		T560	1		T794	1
all_values[34]	468	1			T558	1		T794	7		T644	1
all_values[35]	453	1			T433	1		T794	1		T645	5
all_values[36]	370	1			T568	2		T550	1		T560	4
all_values[37]	400	1			T457	1		T568	2		T550	1
all_values[38]	405	1			T560	2		T482	1		T794	1
all_values[39]	382	1			T457	2		T568	2		T558	2
all_values[40]	486	1			T794	3		T476	2		T850	5
all_values[41]	412	1			T550	1		T560	1		T433	1
all_values[42]	453	1			T457	1		T560	1		T800	1
all_values[43]	445	1			T550	1		T686	1		T560	8
all_values[44]	416	1			T568	1		T558	1		T874	1
all_values[45]	412	1			T457	1		T568	1		T550	1
all_values[46]	413	1			T568	1		T874	1		T560	1
all_values[47]	478	1			T558	1		T686	1		T560	5
all_values[48]	437	1			T457	1		T560	1		T433	1
all_values[49]	438	1			T560	5		T794	2		T645	4