Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3189	1			T549	3		T272	6		T568	6
all_values[1]	3193	1			T271	1		T549	3		T272	7
all_values[2]	3221	1			T271	3		T549	4		T272	6
all_values[3]	3258	1			T271	2		T549	5		T272	7
all_values[4]	3242	1			T271	2		T549	2		T272	12
all_values[5]	3263	1			T271	1		T549	6		T272	3
all_values[6]	3247	1			T549	4		T272	6		T568	5
all_values[7]	3279	1			T549	3		T272	6		T568	5
all_values[8]	3146	1			T271	3		T549	3		T272	6
all_values[9]	3220	1			T271	3		T549	2		T272	10
all_values[10]	3288	1			T271	2		T549	2		T272	7
all_values[11]	3165	1			T271	1		T549	1		T272	5
all_values[12]	3218	1			T549	3		T272	6		T568	5
all_values[13]	3319	1			T271	2		T549	2		T272	8
all_values[14]	3323	1			T549	2		T272	8		T568	5
all_values[15]	3228	1			T271	4		T549	1		T272	6
all_values[16]	3306	1			T271	2		T549	2		T272	3
all_values[17]	3206	1			T271	2		T549	6		T272	9
all_values[18]	3271	1			T271	2		T549	3		T272	7
all_values[19]	3243	1			T271	3		T272	10		T568	2
all_values[20]	3222	1			T271	2		T549	1		T272	7
all_values[21]	3181	1			T271	1		T549	4		T272	10
all_values[22]	3220	1			T271	1		T549	1		T272	4
all_values[23]	3174	1			T271	1		T549	6		T272	8
all_values[24]	3162	1			T271	2		T549	3		T272	7
all_values[25]	3179	1			T549	4		T272	5		T568	5
all_values[26]	3268	1			T271	2		T272	9		T568	5
all_values[27]	3247	1			T549	4		T272	7		T568	2
all_values[28]	3182	1			T549	3		T272	12		T568	3
all_values[29]	3340	1			T271	2		T549	3		T272	4
all_values[30]	3281	1			T549	2		T272	10		T568	2
all_values[31]	3313	1			T271	1		T549	4		T272	7
all_values[32]	3173	1			T271	2		T272	4		T568	2
all_values[33]	3401	1			T271	2		T549	5		T272	8
all_values[34]	3275	1			T271	3		T549	2		T272	12
all_values[35]	3234	1			T271	3		T549	3		T272	4
all_values[36]	3241	1			T271	4		T549	5		T272	8
all_values[37]	3160	1			T549	4		T272	10		T568	1
all_values[38]	3223	1			T271	2		T549	3		T272	5
all_values[39]	3365	1			T271	1		T549	2		T272	5
all_values[40]	3318	1			T271	5		T549	2		T272	9
all_values[41]	3243	1			T549	6		T272	4		T568	3
all_values[42]	3158	1			T271	2		T272	7		T568	2
all_values[43]	3228	1			T271	5		T549	4		T272	4
all_values[44]	3228	1			T549	1		T272	6		T568	8
all_values[45]	3235	1			T271	1		T272	4		T568	4
all_values[46]	3159	1			T271	1		T549	3		T272	5
all_values[47]	3320	1			T271	3		T549	1		T272	7
all_values[48]	3288	1			T271	2		T549	4		T272	8
all_values[49]	3247	1			T271	5		T272	6		T568	3
all_values[50]	3263	1			T271	2		T549	2		T272	6
all_values[51]	3331	1			T271	2		T549	2		T272	7
all_values[52]	3367	1			T271	2		T549	1		T272	8
all_values[53]	3204	1			T271	1		T549	5		T272	8
all_values[54]	3320	1			T271	4		T549	2		T272	12
all_values[55]	3244	1			T271	5		T549	3		T272	10
all_values[56]	3139	1			T271	1		T549	4		T272	6
all_values[57]	3152	1			T549	6		T272	7		T568	3
all_values[58]	3179	1			T271	5		T549	5		T272	9
all_values[59]	3123	1			T271	3		T549	2		T272	3
all_values[60]	3314	1			T271	1		T549	1		T272	8
all_values[61]	3268	1			T271	1		T549	4		T272	5
all_values[62]	3347	1			T271	4		T549	1		T272	4
all_values[63]	3263	1			T549	2		T272	7		T558	5