Unified Coverage Report :: Cond split page

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 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T95,T97,T101
1	1	Covered	T2,T4,T5

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T338,T339,T340
1	0	Not Covered

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T338,T339,T340
0	1	0	Covered	T163,T189,T460
1	0	0	Covered	T338,T339,T340

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T163,T189,T460
0	1	0	Covered	T406,T557,T573
1	0	0	Covered	T95,T96,T97

 LINE       16648
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO0_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T4,T5

 LINE       16649
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO1_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T131,T132,T273

 LINE       16650
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO2_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T131,T132,T273

 LINE       16651
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO3_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T131,T132,T273

 LINE       16652
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO4_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T131,T132,T273

 LINE       16653
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO5_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T131,T132,T273

 LINE       16654
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO6_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T131,T132,T273

 LINE       16655
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO7_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T131,T132,T273

 LINE       16656
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO8_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T131,T132,T273

 LINE       16657
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO9_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T131,T132,T273

 LINE       16658
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO10_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T133,T134,T273

 LINE       16659
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO11_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T133,T134,T273

 LINE       16660
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO12_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T133,T134,T273

 LINE       16661
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO13_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T133,T134,T273

 LINE       16662
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO14_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T133,T134,T273

 LINE       16663
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO15_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T133,T134,T273

 LINE       16664
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO16_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T133,T134,T273

 LINE       16665
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO17_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T133,T134,T273

 LINE       16666
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO18_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T133,T134,T273

 LINE       16667
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO19_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T63,T273,T127

 LINE       16668
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO20_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T63,T273,T127

 LINE       16669
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO21_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T63,T273,T127

 LINE       16670
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO22_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T63,T273,T127

 LINE       16671
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO23_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T63,T273,T127

 LINE       16672
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO24_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T63,T273,T127

 LINE       16673
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO25_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T63,T273,T127

 LINE       16674
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO26_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T63,T273,T127

 LINE       16675
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO27_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T63,T273,T127

 LINE       16676
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO28_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T38,T273,T127

 LINE       16677
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO29_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T38,T273,T127

 LINE       16678
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO30_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T38,T273,T127

 LINE       16679
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO31_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T38,T273,T127

 LINE       16680
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO32_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T38,T273,T127

 LINE       16681
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO33_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T38,T273,T127

 LINE       16682
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO34_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T38,T273,T127

 LINE       16683
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO35_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T38,T273,T127

 LINE       16684
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO36_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T38,T273,T127

 LINE       16685
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO37_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16686
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO38_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16687
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO39_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16688
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO40_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16689
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO41_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16690
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO42_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16691
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO43_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16692
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO44_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16693
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO45_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16694
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO46_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16695
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO47_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16696
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO48_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16697
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO49_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16698
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO50_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16699
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO51_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16700
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO52_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16701
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO53_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16702
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO54_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16703
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO55_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16704
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO56_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16705
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO57_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16706
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO58_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16707
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO59_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16708
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO60_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16709
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO61_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16710
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO62_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16711
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO63_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16712
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO64_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16713
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO65_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16714
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO66_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16715
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO67_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16716
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO68_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T27,T273,T127

 LINE       16717
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO69_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T13,T27,T9

 LINE       16718
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO70_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T13,T273,T127

 LINE       16719
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO71_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T13,T273,T127

 LINE       16720
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO72_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T13,T9,T10

 LINE       16721
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO73_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T13,T9,T10

 LINE       16722
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO74_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T13,T273,T127

 LINE       16723
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO75_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16724
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO76_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16725
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO77_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T58,T273,T127

 LINE       16726
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO78_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T58,T273,T127

 LINE       16727
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO79_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16728
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO80_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T58,T273,T127

 LINE       16729
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO81_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T58,T273,T127

 LINE       16730
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO82_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T58,T273,T127

 LINE       16731
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO83_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T58,T273,T127

 LINE       16732
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO84_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T58,T273,T127

 LINE       16733
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO85_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16734
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO86_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T57,T58,T273

 LINE       16735
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO87_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T57,T273,T127

 LINE       16736
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO88_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16737
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO89_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T57,T273,T127

 LINE       16738
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO90_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T57,T273,T127

 LINE       16739
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO91_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T57,T273,T127

 LINE       16740
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO92_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T59,T273,T127

 LINE       16741
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO93_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T59,T273,T127

 LINE       16742
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO94_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16743
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO95_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T59,T273,T127

 LINE       16744
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO96_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T59,T273,T127

 LINE       16745
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO97_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T59,T273,T127

 LINE       16746
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO98_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T59,T273,T127

 LINE       16747
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO99_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T59,T273,T127

 LINE       16748
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO100_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16749
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO101_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T59,T273,T127

 LINE       16750
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO102_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16751
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO103_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16752
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO104_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16753
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO105_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16754
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO106_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16755
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO107_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T61,T273,T127

 LINE       16756
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO108_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T61,T273,T127

 LINE       16757
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO109_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16758
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO110_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T61,T273,T127

 LINE       16759
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO111_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T61,T273,T127

 LINE       16760
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO112_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T61,T273,T127

 LINE       16761
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO113_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T61,T273,T127

 LINE       16762
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO114_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T61,T273,T127

 LINE       16763
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO115_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16764
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO116_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T61,T273,T127

 LINE       16765
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO117_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16766
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO118_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16767
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO119_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16768
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO120_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16769
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO121_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16770
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO122_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T273,T127

 LINE       16771
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO123_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T273,T127

 LINE       16772
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO124_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16773
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO125_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16774
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO126_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16775
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO127_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T42,T82,T84

 LINE       16776
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO128_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T42,T82,T84

 LINE       16777
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO129_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T42,T82,T84

 LINE       16778
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO130_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T42,T82,T84

 LINE       16779
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO131_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T9,T10,T273

 LINE       16780
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO132_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T9,T10,T273

 LINE       16781
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO133_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319

 LINE       16782
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO134_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T273,T127,T319