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 LINE       1303
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T42,T82,T84
1	0	1	Covered	T42,T82,T208
1	1	0	Covered	T548,T433,T474
1	1	1	Covered	T452,T137,T453

 LINE       1308
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T42,T82,T84
1	0	1	Covered	T82,T291,T292
1	1	0	Covered	T96,T446,T547
1	1	1	Covered	T68,T188,T456

 LINE       1317
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T68,T188,T549
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       1318
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T68,T456,T551
1	1	0	Covered	T649
1	1	1	Covered	T2,T4,T5

 LINE       1319
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T68,T456,T271
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4