Go
back
71 if (offset < NumSrc) begin : gen_assign
72 185/186 ==> assign vld_tree[Pa] = valid_i[offset];
Tests: T131 T132 T319 | T131 T132 T319 | T131 T132 T319 | T131 T132 T319 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T131 T132 T319 | T133 T134 T319 | T133 T134 T319 | T133 T134 T319 | T133 T134 T319 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T133 T134 T319 | T63 T319 T64 | T63 T319 T64 | T63 T319 T64 | T63 T319 T64 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T63 T319 T64 | T38 T65 T319 | T38 T65 T319 | T38 T65 T319 | T38 T65 T319 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T38 T65 T319 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T9 T127 T227 | T127 T190 T191 | T127 T190 T191 | T127 T190 T191 | T127 T190 T191 | T13 T127 T49 | T127 T190 T191 | T127 T190 T191 | T58 T331 T139 | T58 T331 T139 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T57 T58 T331 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T59 T331 T60 | T59 T331 T60 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T59 T331 T60 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T61 T331 T62 | T61 T331 T62 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T61 T331 T62 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T2 T127 T136 | T127 T136 T190 | T127 T190 T191 | T127 T190 T191 | T127 T190 T191 | T84 T285 T192 | T335 T192 T331 | T82 T208 T331 | T42 T192 T331 | T127 T190 T191 | T127 T190 T191 | T127 T190 T191 | T127 T190 T191 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T4 T26 T12 | T66 T319 T235 | T140 T331 T142 | T336 T258 T331 | T5 T258 T192 | T180 T127 T343 | T127 T190 T191 | T121 T148 T294 | T121 T148 T294 | T148 T294 T331 | T148 T294 T331 | T121 T148 T294 | T331 T332 T333 | T326 T327 T331 | T331 T332 T333 | T331 T332 T333 | T127 T190 T191 | T127 T190 T191 | T127 T190 T191 | T328 T127 T184 | T127 T190 T191 | T331 T332 T333 | T320 T331 T337 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T320 T331 T337 | T331 T332 T333 | T320 T331 T337 | T331 T332 T333
73 assign idx_tree[Pa] = offset;
74 186/186 assign max_tree[Pa] = values_i[offset];
Tests: T273 T99 T274 | T131 T132 T273 | T131 T132 T273 | T131 T132 T273 | T131 T132 T273 | T131 T132 T273 | T131 T132 T273 | T131 T132 T273 | T131 T132 T273 | T131 T132 T273 | T133 T134 T273 | T133 T134 T273 | T133 T134 T273 | T133 T134 T273 | T133 T134 T273 | T133 T134 T273 | T133 T134 T273 | T133 T134 T273 | T133 T134 T273 | T63 T273 T127 | T63 T273 T127 | T63 T273 T127 | T63 T273 T127 | T63 T273 T127 | T63 T273 T127 | T63 T273 T127 | T63 T273 T127 | T63 T273 T127 | T38 T273 T127 | T38 T273 T127 | T38 T273 T127 | T38 T273 T127 | T38 T273 T127 | T38 T273 T127 | T38 T273 T127 | T38 T273 T127 | T38 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T13 T27 T9 | T13 T273 T127 | T13 T273 T127 | T13 T9 T10 | T13 T9 T10 | T13 T273 T127 | T273 T127 T319 | T273 T127 T319 | T58 T273 T127 | T58 T273 T127 | T273 T127 T319 | T58 T273 T127 | T58 T273 T127 | T58 T273 T127 | T58 T273 T127 | T58 T273 T127 | T273 T127 T319 | T57 T58 T273 | T57 T273 T127 | T273 T127 T319 | T57 T273 T127 | T57 T273 T127 | T57 T273 T127 | T59 T273 T127 | T59 T273 T127 | T273 T127 T319 | T59 T273 T127 | T59 T273 T127 | T59 T273 T127 | T59 T273 T127 | T59 T273 T127 | T273 T127 T319 | T59 T273 T127 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T61 T273 T127 | T61 T273 T127 | T273 T127 T319 | T61 T273 T127 | T61 T273 T127 | T61 T273 T127 | T61 T273 T127 | T61 T273 T127 | T273 T127 T319 | T61 T273 T127 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T2 T273 T127 | T2 T273 T127 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T42 T82 T84 | T42 T82 T84 | T42 T82 T84 | T42 T82 T84 | T9 T10 T273 | T9 T10 T273 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T4 T26 T7 | T66 T273 T127 | T140 T273 T127 | T42 T82 T84 | T5 T42 T82 | T180 T273 T127 | T273 T127 T319 | T121 T148 T294 | T121 T148 T294 | T121 T148 T294 | T121 T148 T294 | T121 T148 T294 | T273 T127 T319 | T326 T327 T273 | T326 T327 T273 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T328 T273 T127 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319
75 end else begin : gen_tie_off
76 assign vld_tree[Pa] = '0;
77 assign idx_tree[Pa] = '0;
78 assign max_tree[Pa] = '0;
79 end
80 // This creates the node assignments.
81 end else begin : gen_nodes
82 logic sel; // Local helper variable
83 // In case only one of the parents is valid, forward that one
84 // In case both parents are valid, forward the one with higher value
85 185/185(70 unreachable) assign sel = (~vld_tree[C0] & vld_tree[C1]) |
Tests: T2 T4 T5 | T2 T13 T27 | T27 T38 T133 | T2 T13 T27 | T4 T5 T26 | T38 T133 T134 | T27 T38 T273 | T13 T27 T9 | T2 T84 T59 | T4 T5 T26 | T121 T148 T294 | T133 T134 T131 | T38 T133 T134 | T27 T38 T273 | T27 T273 T127 | T13 T27 T9 | T57 T59 T58 | T59 T61 T273 | T2 T84 T61 | T42 T82 T84 | T4 T5 T26 | T121 T148 T294 | T273 T127 T319 | T131 T132 T273 | T133 T134 T131 | T133 T134 T63 | T38 T63 T273 | T27 T38 T273 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T9 T273 | T13 T9 T10 | T57 T58 T273 | T59 T273 T127 | T59 T273 T127 | T61 T273 T127 | T61 T273 T127 | T2 T84 T285 | T9 T42 T82 | T273 T127 T319 | T273 T127 T319 | T4 T5 T26 | T121 T148 T294 | T328 T273 T127 | T273 T127 T319 | T131 T132 T273 | T131 T132 T273 | T133 T134 T131 | T133 T134 T273 | T133 T134 T63 | T63 T273 T127 | T63 T273 T127 | T38 T273 T127 | T38 T273 T127 | T27 T38 T273 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T13 T27 T9 | T13 T9 T10 | T58 T273 T127 | T58 T273 T127 | T57 T58 T273 | T57 T273 T127 | T59 T273 T127 | T59 T273 T127 | T59 T273 T127 | T61 T273 T127 | T61 T273 T127 | T61 T273 T127 | T61 T273 T127 | T2 T273 T127 | T84 T285 T192 | T42 T82 T84 | T9 T10 T273 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T4 T26 T12 | T5 T42 T82 | T121 T148 T294 | T121 T148 T294 | T273 T127 T319 | T328 T273 T127 | T273 T127 T319 | T273 T127 T319 | T131 T132 T273 | T131 T132 T273 | T131 T132 T273 | T131 T132 T273 | T131 T132 T273 | T133 T134 T273 | T133 T134 T273 | T133 T134 T273 | T133 T134 T273 | T133 T134 T63 | T63 T273 T127 | T63 T273 T127 | T63 T273 T127 | T63 T273 T127 | T38 T273 T127 | T38 T273 T127 | T38 T273 T127 | T38 T273 T127 | T27 T38 T273 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T13 T27 T9 | T13 T273 T127 | T13 T9 T10 | T13 T273 T127 | T58 T273 T127 | T58 T273 T127 | T58 T273 T127 | T58 T273 T127 | T58 T273 T127 | T57 T58 T273 | T57 T273 T127 | T57 T273 T127 | T59 T273 T127 | T59 T273 T127 | T59 T273 T127 | T59 T273 T127 | T59 T273 T127 | T273 T127 T319 | T273 T127 T319 | T61 T273 T127 | T61 T273 T127 | T61 T273 T127 | T61 T273 T127 | T61 T273 T127 | T61 T273 T127 | T273 T127 T319 | T273 T127 T319 | T2 T273 T127 | T273 T127 T319 | T42 T82 T84 | T42 T82 T84 | T9 T42 T82 | T9 T10 T273 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T4 T26 T7 | T66 T140 T273 | T5 T42 T82 | T180 T273 T127 | T121 T148 T294 | T121 T148 T294 | T121 T148 T294 | T326 T327 T273 | T273 T127 T319 | T273 T127 T319 | T328 T273 T127 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319
86 (vld_tree[C0] & vld_tree[C1] & logic'(max_tree[C1] > max_tree[C0]));
87 // Forwarding muxes
88 // Note: these ternaries have triggered a synthesis bug in Vivado versions older
89 // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
90 188/188(67 unreachable) assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
Tests: T2 T4 T5 | T2 T13 T27 | T4 T5 T26 | T27 T38 T133 | T2 T13 T27 | T4 T5 T26 | T38 T133 T134 | T27 T38 T65 | T13 T27 T9 | T2 T84 T59 | T4 T5 T26 | T121 T148 T294 | T133 T134 T131 | T38 T133 T134 | T27 T38 T65 | T27 T331 T40 | T13 T27 T9 | T57 T59 T58 | T59 T61 T331 | T2 T84 T61 | T42 T82 T208 | T4 T5 T26 | T121 T148 T294 | T320 T331 T337 | T131 T132 T319 | T133 T134 T131 | T133 T134 T63 | T38 T63 T65 | T27 T38 T65 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T9 T127 | T13 T58 T127 | T57 T58 T331 | T59 T331 T60 | T59 T331 T60 | T61 T331 T62 | T61 T331 T62 | T2 T84 T285 | T42 T82 T208 | T319 T329 T330 | T319 T329 T330 | T4 T5 T26 | T121 T148 T294 | T328 T127 T320 | T320 T331 T337 | T320 T331 T337 | T131 T132 T319 | T131 T132 T319 | T133 T134 T131 | T133 T134 T319 | T133 T134 T63 | T63 T319 T64 | T63 T319 T64 | T38 T65 T319 | T319 T329 T330 | T27 T38 T65 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T9 T127 | T13 T127 T49 | T58 T127 T331 | T331 T332 T333 | T57 T58 T331 | T331 T332 T333 | T59 T331 T60 | T331 T332 T333 | T59 T331 T60 | T61 T331 T62 | T61 T331 T62 | T331 T332 T333 | T61 T331 T62 | T2 T127 T331 | T84 T285 T192 | T42 T82 T208 | T127 T319 T190 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T4 T26 T12 | T5 T336 T258 | T121 T148 T294 | T121 T148 T294 | T127 T331 T190 | T328 T127 T320 | T331 T332 T333 | T320 T331 T337 | T320 T331 T337 | T131 T132 T319 | T131 T132 T319 | T131 T132 T319 | T319 T329 T330 | T131 T132 T319 | T133 T134 T319 | T133 T134 T319 | T319 T329 T330 | T319 T329 T330 | T133 T134 T63 | T63 T319 T64 | T63 T319 T64 | T319 T329 T330 | T63 T319 T64 | T38 T65 T319 | T38 T65 T319 | T319 T329 T330 | T319 T329 T330 | T27 T38 T65 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T9 T127 | T127 T190 T191 | T127 T190 T191 | T13 T127 T49 | T58 T127 T331 | T58 T331 T139 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T57 T58 T331 | T331 T332 T333 | T331 T332 T333 | T59 T331 T60 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T59 T331 T60 | T331 T332 T333 | T331 T332 T333 | T61 T331 T62 | T61 T331 T62 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T61 T331 T62 | T331 T332 T333 | T331 T332 T333 | T2 T127 T136 | T127 T190 T191 | T84 T285 T192 | T82 T208 T335 | T42 T192 T127 | T127 T190 T191 | T127 T319 T190 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T4 T26 T12 | T66 T140 T319 | T5 T336 T258 | T180 T127 T343 | T121 T148 T294 | T148 T294 T331 | T121 T148 T294 | T326 T327 T331 | T127 T331 T190 | T127 T190 T191 | T328 T127 T184 | T320 T331 T337 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T320 T331 T337 | T320 T331 T337
91 188/255 ==> assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
Tests: T2 T4 T5 | T2 T13 T27 | T4 T5 T26 | T27 T38 T133 | T2 T13 T27 | T4 T5 T26 | T38 T133 T134 | T27 T38 T65 | T13 T27 T9 | T2 T84 T59 | T4 T5 T26 | T121 T148 T294 | T133 T134 T131 | T38 T133 T134 | T27 T38 T65 | T27 T331 T40 | T13 T27 T9 | T57 T59 T58 | T59 T61 T331 | T2 T84 T61 | T42 T82 T208 | T4 T5 T26 | T121 T148 T294 | T320 T331 T337 | T131 T132 T319 | T133 T134 T131 | T133 T134 T63 | T38 T63 T65 | T27 T38 T65 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T9 T127 | T13 T58 T127 | T57 T58 T331 | T59 T331 T60 | T59 T331 T60 | T61 T331 T62 | T61 T331 T62 | T2 T84 T285 | T42 T82 T208 | T319 T329 T330 | T319 T329 T330 | T4 T5 T26 | T121 T148 T294 | T328 T127 T320 | T320 T331 T337 | T331 T332 T333 | T131 T132 T319 | T319 T329 T330 | T133 T134 T131 | T133 T134 T319 | T133 T134 T63 | T63 T319 T64 | T63 T319 T64 | T38 T65 T319 | T319 T329 T330 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T9 T127 T227 | T13 T127 T49 | T58 T331 T139 | T331 T332 T333 | T57 T58 T331 | T331 T332 T333 | T59 T331 T60 | T331 T332 T333 | T59 T331 T60 | T61 T331 T62 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T2 T127 T331 | T84 T285 T192 | T42 T82 T208 | T127 T319 T190 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T4 T26 T12 | T5 T258 T180 | T121 T148 T294 | T326 T327 T331 | T127 T190 T191 | T127 T320 T331 | T331 T332 T333 | T320 T331 T337 | T331 T332 T333 | T131 T132 T319 | T131 T132 T319 | T319 T329 T330 | T319 T329 T330 | T131 T132 T319 | T133 T134 T319 | T133 T134 T319 | T319 T329 T330 | T319 T329 T330 | T63 T319 T64 | T63 T319 T64 | T319 T329 T330 | T319 T329 T330 | T63 T319 T64 | T38 T65 T319 | T38 T65 T319 | T319 T329 T330 | T319 T329 T330 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T9 T127 T227 | T127 T190 T191 | T127 T190 T191 | T127 T190 T191 | T58 T331 T139 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T59 T331 T60 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T59 T331 T60 | T331 T332 T333 | T331 T332 T333 | T61 T331 T62 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T127 T136 T190 | T127 T190 T191 | T84 T285 T192 | T82 T208 T331 | T127 T190 T191 | T127 T190 T191 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T319 T329 T330 | T4 T26 T12 | T140 T331 T142 | T5 T258 T192 | T127 T190 T191 | T121 T148 T294 | T148 T294 T331 | T331 T332 T333 | T331 T332 T333 | T127 T190 T191 | T127 T190 T191 | T127 T190 T191 | T320 T331 T337 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333
92 188/255 ==> assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
Tests: T2 T4 T5 | T2 T13 T27 | T4 T5 T26 | T27 T38 T133 | T2 T13 T27 | T4 T5 T26 | T38 T133 T134 | T27 T38 T273 | T13 T27 T9 | T2 T84 T59 | T4 T5 T26 | T121 T148 T294 | T133 T134 T131 | T38 T133 T134 | T27 T38 T273 | T27 T273 T127 | T13 T27 T9 | T57 T59 T58 | T59 T61 T273 | T2 T84 T61 | T42 T82 T84 | T4 T5 T26 | T121 T148 T294 | T273 T127 T319 | T131 T132 T273 | T133 T134 T131 | T133 T134 T63 | T38 T63 T273 | T27 T38 T273 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T9 T273 | T13 T9 T10 | T57 T58 T273 | T59 T273 T127 | T59 T273 T127 | T61 T273 T127 | T61 T273 T127 | T2 T84 T285 | T9 T42 T82 | T273 T127 T319 | T273 T127 T319 | T4 T5 T26 | T121 T148 T294 | T328 T273 T127 | T273 T127 T319 | T273 T127 T319 | T131 T132 T273 | T131 T132 T273 | T133 T134 T131 | T133 T134 T273 | T133 T134 T63 | T63 T273 T127 | T63 T273 T127 | T38 T273 T127 | T38 T273 T127 | T27 T38 T273 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T13 T27 T9 | T13 T9 T10 | T58 T273 T127 | T58 T273 T127 | T57 T58 T273 | T57 T273 T127 | T59 T273 T127 | T59 T273 T127 | T59 T273 T127 | T61 T273 T127 | T61 T273 T127 | T61 T273 T127 | T61 T273 T127 | T2 T273 T127 | T84 T285 T192 | T42 T82 T84 | T9 T10 T273 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T4 T26 T12 | T5 T42 T82 | T121 T148 T294 | T121 T148 T294 | T273 T127 T319 | T328 T273 T127 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T131 T132 T273 | T131 T132 T273 | T131 T132 T273 | T131 T132 T273 | T131 T132 T273 | T133 T134 T273 | T133 T134 T273 | T133 T134 T273 | T133 T134 T273 | T133 T134 T63 | T63 T273 T127 | T63 T273 T127 | T63 T273 T127 | T63 T273 T127 | T38 T273 T127 | T38 T273 T127 | T38 T273 T127 | T38 T273 T127 | T27 T38 T273 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T27 T273 T127 | T13 T27 T9 | T13 T273 T127 | T13 T9 T10 | T13 T273 T127 | T58 T273 T127 | T58 T273 T127 | T58 T273 T127 | T58 T273 T127 | T58 T273 T127 | T57 T58 T273 | T57 T273 T127 | T57 T273 T127 | T59 T273 T127 | T59 T273 T127 | T59 T273 T127 | T59 T273 T127 | T59 T273 T127 | T273 T127 T319 | T273 T127 T319 | T61 T273 T127 | T61 T273 T127 | T61 T273 T127 | T61 T273 T127 | T61 T273 T127 | T61 T273 T127 | T273 T127 T319 | T273 T127 T319 | T2 T273 T127 | T273 T127 T319 | T42 T82 T84 | T42 T82 T84 | T9 T42 T82 | T9 T10 T273 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T4 T26 T7 | T66 T140 T273 | T5 T42 T82 | T180 T273 T127 | T121 T148 T294 | T121 T148 T294 | T121 T148 T294 | T326 T327 T273 | T273 T127 T319 | T273 T127 T319 | T328 T273 T127 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319 | T273 T127 T319
93 end
94 end : gen_level
95 end : gen_tree
96
97
98 // The results can be found at the tree root
99 1/1 assign max_valid_o = vld_tree[0];
Tests: T2 T4 T5
100 1/1 assign max_idx_o = idx_tree[0];
Tests: T2 T4 T5
101 1/1 assign max_value_o = max_tree[0];
Tests: T2 T4 T5
102
103 ////////////////
104 // Assertions //
105 ////////////////
106
107 `ifdef INC_ASSERT
108 //VCS coverage off
109 // pragma coverage off
110
111 // Helper functions for assertions below.
112 function automatic logic [Width-1:0] max_value (input logic [NumSrc-1:0][Width-1:0] values_i,
113 input logic [NumSrc-1:0] valid_i);
114 unreachable logic [Width-1:0] value = '0;
115 unreachable for (int k = 0; k < NumSrc; k++) begin
116 unreachable if (valid_i[k] && values_i[k] > value) begin
117 unreachable value = values_i[k];
118 end
==> MISSING_ELSE
119 end
120 unreachable return value;
121 endfunction : max_value
122
123 function automatic logic [SrcWidth-1:0] max_idx (input logic [NumSrc-1:0][Width-1:0] values_i,
124 input logic [NumSrc-1:0] valid_i);
125 unreachable logic [Width-1:0] value = '0;
126 unreachable logic [SrcWidth-1:0] idx = '0;
127 unreachable for (int k = NumSrc-1; k >= 0; k--) begin
128 unreachable if (valid_i[k] && values_i[k] >= value) begin
129 unreachable value = values_i[k];
130 unreachable idx = k;
131 end
==> MISSING_ELSE
132 end
133 unreachable return idx;
134 endfunction : max_idx
135
136 logic [Width-1:0] max_value_exp;
137 logic [SrcWidth-1:0] max_idx_exp;
138 unreachable assign max_value_exp = max_value(values_i, valid_i);
139 unreachable assign max_idx_exp = max_idx(values_i, valid_i);