Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	139794	1			T94	6		T95	1		T96	3
values[2]	9737	1			T279	1		T453	1		T546	5
values[3]	3713	1			T470	173		T462	18		T797	78
values[4]	2342	1			T470	127		T462	9		T797	37
values[5]	1378	1			T470	89		T462	11		T797	10
values[6]	1000	1			T470	39		T462	5		T797	2
values[7]	767	1			T470	24		T462	6		T793	8
values[8]	546	1			T470	4		T462	6		T793	6
values[9]	435	1			T470	2		T462	16		T831	2
values[10]	362	1			T462	7		T831	2		T832	5
values[11]	353	1			T462	4		T831	2		T832	5
values[12]	312	1			T462	22		T832	10		T823	1
values[13]	329	1			T462	8		T832	7		T466	14
values[14]	303	1			T462	7		T832	5		T466	14
values[15]	301	1			T462	5		T832	12		T466	16
values[16]	253	1			T462	7		T832	10		T466	16
values[17]	280	1			T462	5		T832	9		T466	13
values[18]	259	1			T462	7		T832	10		T466	7
values[19]	277	1			T462	2		T832	7		T466	4
values[20]	313	1			T462	6		T832	4		T466	9
values[21]	267	1			T462	8		T832	19		T466	8
values[22]	255	1			T462	6		T832	7		T466	10
values[23]	249	1			T462	4		T832	4		T466	7
values[24]	266	1			T462	6		T832	4		T466	3
values[25]	286	1			T462	4		T832	3		T466	6
values[26]	270	1			T462	7		T832	8		T466	5
values[27]	295	1			T462	13		T832	3		T466	19
values[28]	241	1			T462	2		T832	5		T466	3
values[29]	252	1			T462	5		T832	9		T466	6
values[30]	231	1			T462	7		T832	11		T466	7
values[31]	190	1			T462	7		T832	7		T466	7
values[32]	265	1			T462	5		T832	11		T466	16
values[33]	250	1			T462	6		T832	5		T466	6
values[34]	272	1			T462	6		T832	5		T466	3
values[35]	236	1			T462	6		T832	6		T466	4
values[36]	226	1			T832	4		T466	3		T490	1
values[37]	246	1			T832	7		T466	4		T490	1
values[38]	232	1			T832	6		T466	5		T490	1
values[39]	254	1			T832	3		T466	3		T490	1
values[40]	283	1			T832	14		T466	6		T490	1
values[41]	231	1			T832	9		T466	13		T490	1
values[42]	255	1			T832	8		T466	7		T490	1
values[43]	275	1			T832	4		T466	7		T490	1
values[44]	225	1			T832	12		T466	3		T490	1
values[45]	181	1			T832	7		T466	5		T490	1
values[46]	226	1			T832	4		T466	14		T490	1
values[47]	232	1			T832	8		T466	8		T490	1
values[48]	230	1			T832	3		T466	15		T490	1
values[49]	245	1			T466	19		T490	1		T495	7
values[50]	216	1			T466	9		T490	1		T495	4
values[51]	171	1			T466	7		T490	1		T495	8
values[52]	225	1			T466	6		T490	1		T495	5
values[53]	215	1			T466	12		T490	1		T495	3
values[54]	225	1			T466	6		T490	1		T495	4
values[55]	199	1			T466	8		T490	1		T495	11
values[56]	180	1			T466	4		T490	1		T495	10
values[57]	183	1			T466	8		T490	1		T495	5
values[58]	178	1			T466	2		T490	1		T495	7
values[59]	160	1			T466	4		T490	1		T495	3
values[60]	171	1			T490	1		T495	12		T515	2
values[61]	179	1			T490	1		T495	3		T515	11
values[62]	158	1			T490	1		T495	12		T515	3
values[63]	166	1			T490	1		T495	9		T807	1
values[64]	122	1			T490	1		T495	9		T807	1
values[65]	75	1			T490	1		T807	1		T532	1
values[66]	104	1			T490	1		T807	1		T532	1
values[67]	124	1			T490	1		T807	1		T532	1
values[68]	82	1			T490	1		T807	1		T532	1
values[69]	63	1			T490	1		T807	1		T532	1
values[70]	70	1			T490	1		T807	1		T532	1
values[71]	59	1			T490	1		T807	1		T532	1
values[72]	55	1			T490	1		T807	1		T532	2
values[73]	54	1			T490	1		T807	1		T532	1
values[74]	55	1			T490	1		T807	1		T532	1
values[75]	32	1			T490	1		T807	1		T532	1
values[76]	41	1			T490	1		T807	1		T532	1
values[77]	34	1			T490	1		T807	1		T532	1
values[78]	22	1			T490	1		T807	1		T532	1
values[79]	24	1			T490	1		T807	1		T532	1
values[80]	24	1			T490	1		T807	1		T532	1
values[81]	22	1			T490	1		T807	1		T532	1
values[82]	24	1			T490	1		T807	1		T532	1
values[83]	34	1			T490	1		T807	1		T532	1
values[84]	30	1			T490	1		T807	1		T532	1
values[85]	44	1			T490	1		T807	1		T532	1
values[86]	38	1			T490	1		T807	4		T532	1
values[87]	31	1			T490	1		T807	1		T532	1
values[88]	47	1			T490	1		T807	8		T532	1
values[89]	32	1			T490	1		T807	2		T532	1
values[90]	35	1			T490	3		T807	5		T532	1
values[91]	41	1			T490	10		T807	2		T532	1
values[92]	47	1			T490	5		T807	5		T532	1
values[93]	34	1			T490	2		T807	6		T532	1
values[94]	44	1			T490	2		T807	1		T532	1
values[95]	29	1			T490	1		T807	3		T532	3
values[96]	31	1			T490	3		T807	5		T532	2
values[97]	31	1			T490	1		T807	4		T532	2
values[98]	38	1			T490	3		T807	2		T532	8
values[99]	27	1			T490	3		T807	2		T532	1
values[100]	37	1			T490	1		T807	1		T532	7
values[101]	36	1			T490	2		T807	4		T532	3
values[102]	36	1			T490	1		T807	1		T532	4
values[103]	36	1			T490	2		T807	3		T532	2
values[104]	26	1			T490	1		T807	5		T532	2
values[105]	24	1			T490	1		T807	6		T532	1
values[106]	38	1			T490	4		T807	2		T532	2
values[107]	37	1			T490	6		T807	2		T532	2
values[108]	36	1			T490	5		T807	2		T532	1
values[109]	36	1			T490	3		T807	3		T532	2
values[110]	34	1			T490	2		T807	4		T532	3
values[111]	32	1			T490	1		T807	4		T532	2
values[112]	30	1			T490	1		T807	1		T532	2
values[113]	36	1			T490	1		T807	1		T532	2
values[114]	34	1			T490	2		T807	7		T532	1
values[115]	20	1			T490	2		T807	1		T532	1
values[116]	38	1			T490	7		T807	3		T532	6
values[117]	29	1			T490	2		T807	1		T532	1
values[118]	23	1			T490	3		T807	1		T532	3
values[119]	28	1			T490	5		T807	1		T532	1
values[120]	22	1			T490	1		T807	2		T532	1
values[121]	26	1			T490	1		T807	1		T532	2
values[122]	25	1			T490	2		T807	1		T532	2
values[123]	26	1			T490	2		T807	2		T532	3
values[124]	19	1			T490	1		T807	1		T532	1
values[125]	27	1			T490	2		T807	1		T532	1
values[126]	41	1			T490	1		T807	1		T532	5
values[127]	477	1			T490	27		T807	32		T532	26
values[128]	4404	1			T490	249		T807	312		T532	278