Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.14 95.50 93.91 95.52 94.84 97.53 99.55


Total tests in report: 2926
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
40.64 40.64 49.63 49.63 49.45 49.45 22.25 22.25 64.15 64.15 58.22 58.22 0.13 0.13 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3625868271
50.74 10.10 58.86 9.23 60.04 10.59 27.75 5.51 72.74 8.58 84.44 26.22 0.59 0.46 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.4072822531
56.07 5.33 70.16 11.30 67.60 7.56 30.90 3.14 82.74 10.00 84.44 0.00 0.59 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.3035571146
59.61 3.54 70.16 0.00 67.60 0.00 30.90 0.00 82.74 0.00 84.44 0.00 21.84 21.25 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.480210053
62.92 3.31 74.93 4.77 68.65 1.05 36.44 5.55 82.91 0.17 84.44 0.00 30.16 8.32 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3573501400
65.99 3.07 79.73 4.80 72.45 3.80 39.97 3.52 84.63 1.72 88.99 4.55 30.16 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.912180358
68.79 2.80 79.73 0.00 72.45 0.00 56.48 16.51 84.63 0.00 89.16 0.17 30.27 0.11 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3866641289
71.27 2.48 79.73 0.00 73.51 1.05 56.48 0.00 84.68 0.05 89.16 0.00 44.06 13.79 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.1037241506
73.33 2.06 81.03 1.30 75.48 1.98 61.24 4.76 86.02 1.34 89.51 0.35 46.69 2.63 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.657642451
75.36 2.03 81.03 0.00 75.64 0.16 61.24 0.00 86.05 0.03 89.51 0.00 58.69 12.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2727548900
77.24 1.88 81.03 0.00 75.64 0.00 61.24 0.00 86.05 0.00 89.51 0.00 69.96 11.27 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2231519793
78.65 1.41 83.61 2.58 76.15 0.51 65.79 4.55 86.34 0.28 90.03 0.52 69.96 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.2469476565
80.00 1.35 85.99 2.38 78.09 1.93 66.90 1.11 89.03 2.69 90.03 0.00 69.96 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.2390510873
81.28 1.28 86.11 0.12 78.17 0.08 74.04 7.14 89.20 0.17 90.21 0.17 69.96 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.2200896495
82.48 1.20 86.11 0.00 78.18 0.01 74.04 0.00 89.20 0.00 90.21 0.00 77.14 7.18 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.2540541043
83.59 1.11 87.46 1.35 78.93 0.75 76.96 2.92 90.30 1.10 90.73 0.52 77.15 0.01 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.3129546886
84.57 0.98 87.46 0.00 78.93 0.00 82.83 5.87 90.30 0.00 90.73 0.00 77.15 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.2728888008
85.54 0.98 88.15 0.69 83.37 4.44 82.83 0.00 90.37 0.06 90.73 0.00 77.82 0.67 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.1171468917
86.33 0.78 88.15 0.00 83.37 0.00 82.83 0.00 90.37 0.00 90.73 0.00 82.52 4.70 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.1858163073
87.07 0.74 88.44 0.29 83.49 0.13 82.84 0.01 90.54 0.17 94.58 3.85 82.52 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.538963901
87.81 0.74 89.07 0.64 84.16 0.67 84.40 1.55 91.07 0.53 95.63 1.05 82.52 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.2507037548
88.34 0.54 89.86 0.79 84.90 0.74 84.69 0.29 91.94 0.88 96.15 0.52 82.52 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4294345177
88.84 0.50 90.21 0.34 84.99 0.09 84.69 0.01 91.94 0.00 96.15 0.00 85.08 2.56 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.1026373294
89.33 0.48 90.21 0.00 85.42 0.43 84.69 0.00 92.06 0.11 96.15 0.00 87.44 2.36 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.3698777742
89.76 0.43 90.90 0.69 86.56 1.13 85.18 0.49 92.33 0.28 96.15 0.00 87.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.1025006786
90.19 0.43 90.90 0.00 86.56 0.00 85.18 0.00 92.33 0.00 96.15 0.00 90.02 2.58 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.1660008466
90.62 0.43 90.91 0.01 86.56 0.01 87.57 2.39 92.33 0.00 96.33 0.17 90.02 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.610991903
91.03 0.41 91.83 0.92 86.96 0.40 88.38 0.81 92.67 0.34 96.33 0.00 90.02 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.157332516
91.43 0.40 91.87 0.03 87.63 0.66 88.38 0.00 92.69 0.02 96.33 0.00 91.72 1.69 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.666327047
91.78 0.35 91.87 0.00 87.70 0.07 88.38 0.00 92.72 0.03 96.33 0.00 93.71 2.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.1520394777
92.11 0.33 92.62 0.76 88.01 0.31 89.04 0.66 92.90 0.18 96.33 0.00 93.76 0.05 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3349883346
92.39 0.28 93.08 0.45 88.51 0.50 89.27 0.23 93.41 0.51 96.33 0.00 93.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.392872870
92.67 0.28 93.84 0.76 88.78 0.27 89.58 0.31 93.74 0.33 96.33 0.00 93.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.3605472795
92.92 0.25 93.84 0.00 88.84 0.06 89.58 0.00 93.74 0.00 96.33 0.00 95.22 1.46 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.2802149971
93.13 0.20 93.84 0.00 88.84 0.00 90.80 1.22 93.74 0.00 96.33 0.00 95.22 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.1925534602
93.29 0.16 93.84 0.00 88.84 0.00 91.76 0.96 93.74 0.00 96.33 0.00 95.22 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1723482921
93.44 0.15 93.93 0.10 89.62 0.79 91.78 0.02 93.77 0.02 96.33 0.00 95.22 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.3766778177
93.60 0.15 93.93 0.00 90.54 0.91 91.78 0.00 93.77 0.00 96.33 0.00 95.23 0.01 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.853124778
93.74 0.15 93.93 0.00 90.56 0.03 91.78 0.00 93.77 0.00 96.33 0.00 96.08 0.85 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.4288589820
93.86 0.12 93.93 0.00 90.56 0.00 92.50 0.73 93.77 0.00 96.33 0.00 96.08 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.4277916112
93.98 0.12 93.99 0.06 90.76 0.19 92.79 0.29 93.94 0.17 96.33 0.00 96.08 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.2042332230
94.10 0.12 94.20 0.21 91.08 0.32 92.96 0.17 93.94 0.00 96.33 0.00 96.08 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.902598009
94.21 0.11 94.24 0.04 91.24 0.16 92.96 0.01 93.96 0.02 96.33 0.00 96.51 0.43 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.2229516824
94.31 0.10 94.24 0.00 91.24 0.00 92.96 0.00 93.96 0.00 96.33 0.00 97.12 0.61 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2860624614
94.41 0.10 94.25 0.01 91.51 0.27 92.98 0.01 94.26 0.31 96.33 0.00 97.12 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.151679639
94.49 0.09 94.25 0.00 91.55 0.05 92.98 0.00 94.26 0.00 96.33 0.00 97.59 0.47 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.1541470094
94.56 0.07 94.35 0.11 91.59 0.04 93.20 0.22 94.31 0.05 96.33 0.00 97.59 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.2734773670
94.63 0.06 94.35 0.00 91.68 0.08 93.20 0.00 94.31 0.00 96.33 0.00 97.89 0.29 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.148161972
94.69 0.06 94.36 0.01 91.69 0.02 93.36 0.17 94.31 0.00 96.50 0.17 97.89 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.4167605194
94.74 0.06 94.36 0.00 91.69 0.00 93.70 0.33 94.31 0.00 96.50 0.00 97.89 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1016560128
94.80 0.06 94.38 0.03 91.72 0.02 93.78 0.08 94.34 0.02 96.68 0.17 97.89 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.2755093582
94.85 0.05 94.38 0.00 91.72 0.00 93.78 0.00 94.34 0.00 96.68 0.00 98.19 0.31 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.1778373621
94.90 0.05 94.38 0.00 92.01 0.29 93.78 0.00 94.34 0.00 96.68 0.00 98.19 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.3371200209
94.94 0.05 94.42 0.03 92.02 0.01 93.83 0.05 94.34 0.01 96.85 0.17 98.19 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.2541485118
94.99 0.05 94.42 0.00 92.15 0.13 93.83 0.00 94.49 0.15 96.85 0.00 98.19 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2454493433
95.03 0.04 94.42 0.01 92.17 0.02 94.04 0.21 94.52 0.02 96.85 0.00 98.19 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.4154332190
95.08 0.04 94.50 0.07 92.17 0.00 94.23 0.18 94.52 0.01 96.85 0.00 98.19 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.1964228426
95.12 0.04 94.51 0.01 92.19 0.01 94.43 0.20 94.52 0.00 96.85 0.00 98.21 0.02 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.2215904952
95.16 0.04 94.52 0.01 92.20 0.01 94.43 0.00 94.55 0.02 97.03 0.17 98.23 0.01 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2269459854
95.19 0.04 94.52 0.01 92.22 0.02 94.43 0.00 94.56 0.01 97.20 0.17 98.24 0.01 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.121346763
95.23 0.04 94.53 0.01 92.23 0.01 94.43 0.01 94.56 0.01 97.38 0.17 98.25 0.01 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.3455523361
95.27 0.04 94.53 0.01 92.24 0.01 94.44 0.01 94.57 0.01 97.55 0.17 98.26 0.01 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.3751257530
95.30 0.03 94.57 0.03 92.32 0.07 94.44 0.00 94.58 0.01 97.55 0.00 98.33 0.07 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.4174580320
95.33 0.03 94.64 0.07 92.39 0.07 94.44 0.00 94.61 0.03 97.55 0.00 98.33 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.3414543527
95.36 0.03 94.64 0.01 92.46 0.07 94.47 0.03 94.68 0.06 97.55 0.00 98.33 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3718078101
95.38 0.03 94.67 0.02 92.60 0.14 94.47 0.00 94.68 0.00 97.55 0.00 98.33 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.2608354345
95.41 0.03 94.67 0.00 92.76 0.16 94.47 0.00 94.68 0.00 97.55 0.00 98.33 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.2080911531
95.44 0.03 94.74 0.07 92.79 0.03 94.48 0.01 94.73 0.05 97.55 0.00 98.33 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.1319545611
95.46 0.02 94.74 0.00 92.79 0.00 94.62 0.14 94.73 0.00 97.55 0.00 98.33 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.332014282
95.48 0.02 94.78 0.04 92.81 0.02 94.67 0.05 94.74 0.02 97.55 0.00 98.34 0.01 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2156281307
95.50 0.02 94.79 0.01 92.83 0.02 94.76 0.09 94.74 0.00 97.55 0.00 98.34 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.4069804733
95.52 0.02 94.79 0.00 92.89 0.06 94.76 0.00 94.74 0.00 97.55 0.00 98.40 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1828043398
95.54 0.02 94.80 0.01 92.92 0.03 94.81 0.05 94.76 0.02 97.55 0.00 98.40 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.74405893
95.56 0.02 94.80 0.00 93.02 0.10 94.81 0.00 94.76 0.00 97.55 0.00 98.40 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.3802580878
95.57 0.01 94.80 0.00 93.02 0.00 94.90 0.09 94.76 0.00 97.55 0.00 98.40 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.249769691
95.59 0.01 94.80 0.00 93.03 0.01 94.90 0.00 94.76 0.00 97.55 0.00 98.47 0.07 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.4173781964
95.60 0.01 94.80 0.00 93.03 0.00 94.97 0.07 94.76 0.00 97.55 0.00 98.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.14377772
95.61 0.01 94.80 0.01 93.07 0.04 95.00 0.03 94.76 0.00 97.55 0.00 98.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.2633485081
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96.05 0.01 94.93 0.00 93.91 0.01 95.50 0.00 94.84 0.00 97.55 0.00 99.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.12899734
96.05 0.01 94.93 0.00 93.91 0.00 95.50 0.01 94.84 0.00 97.55 0.00 99.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.2956055049
96.05 0.01 94.93 0.00 93.91 0.00 95.51 0.01 94.84 0.00 97.55 0.00 99.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.433293891
96.05 0.01 94.93 0.00 93.91 0.00 95.51 0.01 94.84 0.00 97.55 0.00 99.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.1818629013
96.05 0.01 94.93 0.00 93.91 0.00 95.51 0.01 94.84 0.00 97.55 0.00 99.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.2077737101
96.05 0.01 94.93 0.00 93.91 0.00 95.51 0.01 94.84 0.00 97.55 0.00 99.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.3653382543
96.05 0.01 94.93 0.00 93.91 0.00 95.52 0.01 94.84 0.00 97.55 0.00 99.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1732524194
96.05 0.01 94.93 0.00 93.91 0.00 95.52 0.01 94.84 0.00 97.55 0.00 99.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.338130025

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.3613660696
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.2607263137
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.3600566947
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.446289631
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.27428673
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.561121023
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.291083051
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.3209237034
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.628825407
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.150344000
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2998267575
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1127016569
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.3328670890
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2547875943
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.476833129
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.3242395757
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1872744899
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.1776306021
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.2939831347
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1664947146
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.2402573661
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.1686168256
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1273537640
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.1565380567
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.3317345465
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.3516861048
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.2222648911
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.3429862524
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.1303024351
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.612752685
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2235336414
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2615353282
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.1832416639
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.77528096
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.2402224585
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.2871434574
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.73446062
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.132490769
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.3248119860
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.3454625641
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1523478934
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1172585704
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.1426927849
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.371071932
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.1244677810
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.2168026167
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.2528468096
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.1964269361
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.424452201
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3317278076
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2980124654
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.3687870754
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3998922273
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1143439089
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.3698658996
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2720350138
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.2659314519
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.842818547
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.792823189
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2137368056
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.769609516
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.1977186336
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.2162091132
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.64473249
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.3957080614
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.2392496319
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.2020712044
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.4261297082
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.2680031056
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2557460502
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3635648720
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.2678828425
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.499737911
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3806072392
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3266072904
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.3621118355
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.4240482903
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.3187048880
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.2634478842
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.1327325317
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.1159586995
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2252651704
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2248219191
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.52273315
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.4196673699
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.95749537
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.1520307648
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.3548666135
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.2693617234
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.2682162231
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.438565144
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1461903544
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.46884848
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.244859353
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3646279716
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1572376618
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.2820736499
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.1161593198
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.3543028413
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.1100417874
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.2568777503
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.581301842
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.236631516
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.1018226178
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.404285136
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.617388753
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.2228894348
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/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.3280561579
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.795462351
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.3431608790
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Total test records in report: 2926
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TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.3209232893 Aug 29 03:30:19 PM UTC 24 Aug 29 03:32:15 PM UTC 24 2949405074 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.442636659 Aug 29 03:33:19 PM UTC 24 Aug 29 03:36:50 PM UTC 24 3492512300 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.1646036432 Aug 29 03:34:37 PM UTC 24 Aug 29 03:37:44 PM UTC 24 2866074686 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.4263993757 Aug 29 03:34:06 PM UTC 24 Aug 29 03:38:29 PM UTC 24 2601881748 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.1997812724 Aug 29 03:35:23 PM UTC 24 Aug 29 03:38:47 PM UTC 24 2736025750 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.3203356228 Aug 29 03:34:17 PM UTC 24 Aug 29 03:38:55 PM UTC 24 2803951600 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3625868271 Aug 29 03:33:57 PM UTC 24 Aug 29 03:39:17 PM UTC 24 3638170991 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_vbus.3785068547 Aug 29 03:34:08 PM UTC 24 Aug 29 03:39:32 PM UTC 24 2901210676 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.2042332230 Aug 29 03:35:05 PM UTC 24 Aug 29 03:39:43 PM UTC 24 4193732840 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.2469476565 Aug 29 03:35:41 PM UTC 24 Aug 29 03:40:00 PM UTC 24 2924496878 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.2180587706 Aug 29 03:35:02 PM UTC 24 Aug 29 03:40:03 PM UTC 24 3414965188 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1764234312 Aug 29 03:35:54 PM UTC 24 Aug 29 03:40:07 PM UTC 24 2510732740 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.2897893004 Aug 29 03:34:53 PM UTC 24 Aug 29 03:40:27 PM UTC 24 3649405830 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.4154332190 Aug 29 03:35:04 PM UTC 24 Aug 29 03:40:40 PM UTC 24 3420177184 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.3728950066 Aug 29 03:32:15 PM UTC 24 Aug 29 03:40:56 PM UTC 24 3902010520 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1941641676 Aug 29 03:35:43 PM UTC 24 Aug 29 03:41:15 PM UTC 24 3336397924 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_entropy.1931543796 Aug 29 03:35:49 PM UTC 24 Aug 29 03:41:26 PM UTC 24 3222379858 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.74405893 Aug 29 03:33:47 PM UTC 24 Aug 29 03:41:32 PM UTC 24 4201913694 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.3129546886 Aug 29 03:33:05 PM UTC 24 Aug 29 03:41:45 PM UTC 24 5146231688 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.157332516 Aug 29 03:34:32 PM UTC 24 Aug 29 03:42:35 PM UTC 24 3813723461 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3718078101 Aug 29 03:35:58 PM UTC 24 Aug 29 03:42:39 PM UTC 24 3774139378 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1866905606 Aug 29 03:40:23 PM UTC 24 Aug 29 03:42:52 PM UTC 24 3271459523 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.277359170 Aug 29 03:41:05 PM UTC 24 Aug 29 03:42:53 PM UTC 24 2113024348 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.413552713 Aug 29 03:39:31 PM UTC 24 Aug 29 03:42:57 PM UTC 24 2826873957 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2662185839 Aug 29 03:38:50 PM UTC 24 Aug 29 03:43:31 PM UTC 24 2904273558 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.409770550 Aug 29 03:41:11 PM UTC 24 Aug 29 03:43:41 PM UTC 24 2765695821 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.3284827870 Aug 29 03:34:07 PM UTC 24 Aug 29 03:43:53 PM UTC 24 4360968616 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1723482921 Aug 29 03:39:36 PM UTC 24 Aug 29 03:43:55 PM UTC 24 3143867649 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3058219253 Aug 29 03:41:01 PM UTC 24 Aug 29 03:44:00 PM UTC 24 3199539217 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.1656138868 Aug 29 03:35:01 PM UTC 24 Aug 29 03:44:10 PM UTC 24 4074992508 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.995943103 Aug 29 03:35:04 PM UTC 24 Aug 29 03:44:15 PM UTC 24 4304410006 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_rand_baudrate.3650126189 Aug 29 03:35:47 PM UTC 24 Aug 29 03:44:21 PM UTC 24 3917488428 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.1493955064 Aug 29 03:35:04 PM UTC 24 Aug 29 03:44:37 PM UTC 24 3952249756 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1311793856 Aug 29 03:40:59 PM UTC 24 Aug 29 03:44:42 PM UTC 24 3631599420 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3098700364 Aug 29 03:33:48 PM UTC 24 Aug 29 03:45:24 PM UTC 24 5960905006 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.20885145 Aug 29 03:35:23 PM UTC 24 Aug 29 03:45:31 PM UTC 24 5108728728 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3866641289 Aug 29 03:35:43 PM UTC 24 Aug 29 03:45:35 PM UTC 24 4022930050 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.3782332297 Aug 29 03:35:22 PM UTC 24 Aug 29 03:45:42 PM UTC 24 4160721360 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.3147347944 Aug 29 03:34:09 PM UTC 24 Aug 29 03:45:50 PM UTC 24 6051524305 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.2796692676 Aug 29 03:42:01 PM UTC 24 Aug 29 03:45:50 PM UTC 24 2678833664 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.1162494645 Aug 29 03:35:01 PM UTC 24 Aug 29 03:46:00 PM UTC 24 4645542090 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2689483580 Aug 29 03:37:21 PM UTC 24 Aug 29 03:46:42 PM UTC 24 4242223844 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.1930415604 Aug 29 03:35:58 PM UTC 24 Aug 29 03:47:16 PM UTC 24 4487655412 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.4237465264 Aug 29 03:35:47 PM UTC 24 Aug 29 03:47:17 PM UTC 24 4538559746 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.1179259189 Aug 29 03:34:33 PM UTC 24 Aug 29 03:47:33 PM UTC 24 5356476126 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.69966747 Aug 29 03:42:22 PM UTC 24 Aug 29 03:48:05 PM UTC 24 4202267800 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.328334825 Aug 29 03:42:49 PM UTC 24 Aug 29 03:48:13 PM UTC 24 4542065850 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.4277916112 Aug 29 03:38:46 PM UTC 24 Aug 29 03:48:13 PM UTC 24 5624084036 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1433696038 Aug 29 03:35:41 PM UTC 24 Aug 29 03:48:48 PM UTC 24 5130726824 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3234396420 Aug 29 03:35:57 PM UTC 24 Aug 29 03:50:12 PM UTC 24 5968230052 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3981442757 Aug 29 03:34:57 PM UTC 24 Aug 29 03:50:36 PM UTC 24 8006950415 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.2755093582 Aug 29 03:42:24 PM UTC 24 Aug 29 03:51:38 PM UTC 24 4752666140 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access.317336940 Aug 29 03:35:02 PM UTC 24 Aug 29 03:51:54 PM UTC 24 5396365688 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.4018057723 Aug 29 03:42:43 PM UTC 24 Aug 29 03:51:57 PM UTC 24 6578605608 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.142020707 Aug 29 03:46:41 PM UTC 24 Aug 29 03:52:15 PM UTC 24 2978776790 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1132090941 Aug 29 03:35:54 PM UTC 24 Aug 29 03:52:17 PM UTC 24 5095013891 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1612351323 Aug 29 03:47:01 PM UTC 24 Aug 29 03:52:26 PM UTC 24 3316768060 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_idle.3555997065 Aug 29 03:49:51 PM UTC 24 Aug 29 03:53:00 PM UTC 24 2739931704 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2175722721 Aug 29 03:35:10 PM UTC 24 Aug 29 03:53:12 PM UTC 24 5985934197 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.917494404 Aug 29 03:46:59 PM UTC 24 Aug 29 03:53:18 PM UTC 24 3300463640 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3939225124 Aug 29 03:48:22 PM UTC 24 Aug 29 03:53:21 PM UTC 24 3083128392 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.2734773670 Aug 29 03:48:13 PM UTC 24 Aug 29 03:53:55 PM UTC 24 3385877874 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.1479982720 Aug 29 03:39:36 PM UTC 24 Aug 29 03:53:59 PM UTC 24 8915145567 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.3094746318 Aug 29 03:49:55 PM UTC 24 Aug 29 03:54:28 PM UTC 24 2702786454 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.4126141134 Aug 29 03:46:46 PM UTC 24 Aug 29 03:54:45 PM UTC 24 8115997892 ps
T659 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.3665341148 Aug 29 03:49:45 PM UTC 24 Aug 29 03:54:52 PM UTC 24 2801290937 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.657642451 Aug 29 03:49:53 PM UTC 24 Aug 29 03:54:59 PM UTC 24 2695433176 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.828655659 Aug 29 03:47:00 PM UTC 24 Aug 29 03:55:18 PM UTC 24 7104393000 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.877648080 Aug 29 03:49:51 PM UTC 24 Aug 29 03:55:34 PM UTC 24 3158803000 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2218072436 Aug 29 03:47:57 PM UTC 24 Aug 29 03:56:12 PM UTC 24 5343447260 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.911655884 Aug 29 03:37:25 PM UTC 24 Aug 29 03:56:21 PM UTC 24 7393117800 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1422015775 Aug 29 03:38:50 PM UTC 24 Aug 29 03:56:32 PM UTC 24 6678692382 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1443787651 Aug 29 03:46:19 PM UTC 24 Aug 29 03:56:28 PM UTC 24 4392967720 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.3194902250 Aug 29 03:34:58 PM UTC 24 Aug 29 03:56:33 PM UTC 24 9546296476 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.2200896495 Aug 29 03:41:08 PM UTC 24 Aug 29 03:56:33 PM UTC 24 9184162750 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3830699995 Aug 29 03:42:50 PM UTC 24 Aug 29 03:56:43 PM UTC 24 6684434560 ps
T669 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2335239847 Aug 29 03:47:34 PM UTC 24 Aug 29 03:57:07 PM UTC 24 5050736842 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.4245486952 Aug 29 03:44:07 PM UTC 24 Aug 29 03:57:17 PM UTC 24 8237096654 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3151711827 Aug 29 03:47:58 PM UTC 24 Aug 29 03:57:28 PM UTC 24 18986806334 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.841828815 Aug 29 03:47:32 PM UTC 24 Aug 29 03:57:44 PM UTC 24 5540486930 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.3615687449 Aug 29 03:53:39 PM UTC 24 Aug 29 03:58:01 PM UTC 24 2849660344 ps
T660 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.356698420 Aug 29 03:46:43 PM UTC 24 Aug 29 03:58:02 PM UTC 24 7965158448 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.17050997 Aug 29 03:48:02 PM UTC 24 Aug 29 03:58:07 PM UTC 24 3498343500 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.1926316911 Aug 29 03:49:55 PM UTC 24 Aug 29 03:58:09 PM UTC 24 3908896536 ps
T885 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_entropy.262489179 Aug 29 03:53:14 PM UTC 24 Aug 29 03:58:26 PM UTC 24 2779901336 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3209225476 Aug 29 03:38:45 PM UTC 24 Aug 29 03:58:26 PM UTC 24 6808365890 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.3165195920 Aug 29 03:49:47 PM UTC 24 Aug 29 03:58:33 PM UTC 24 5228826624 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1933340620 Aug 29 03:52:13 PM UTC 24 Aug 29 03:58:54 PM UTC 24 4050905072 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.1805154770 Aug 29 03:53:13 PM UTC 24 Aug 29 03:59:09 PM UTC 24 3389767758 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2808168971 Aug 29 03:55:50 PM UTC 24 Aug 29 03:59:43 PM UTC 24 2894785740 ps
T886 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3218550858 Aug 29 03:46:58 PM UTC 24 Aug 29 03:59:56 PM UTC 24 10211777604 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.10761712 Aug 29 03:48:14 PM UTC 24 Aug 29 04:00:08 PM UTC 24 4388411071 ps
T629 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.3159518184 Aug 29 03:55:49 PM UTC 24 Aug 29 04:01:29 PM UTC 24 2851134580 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.4069804733 Aug 29 03:34:25 PM UTC 24 Aug 29 04:01:49 PM UTC 24 8401036582 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.640828554 Aug 29 03:49:34 PM UTC 24 Aug 29 04:02:16 PM UTC 24 4615964520 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.3043468867 Aug 29 03:33:30 PM UTC 24 Aug 29 04:02:46 PM UTC 24 8218624386 ps
T661 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.2918842423 Aug 29 03:58:23 PM UTC 24 Aug 29 04:02:46 PM UTC 24 3505754936 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.1818629013 Aug 29 03:54:06 PM UTC 24 Aug 29 04:02:56 PM UTC 24 3356552288 ps
T662 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.912586958 Aug 29 03:58:22 PM UTC 24 Aug 29 04:03:12 PM UTC 24 3504043880 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.3274582906 Aug 29 04:00:13 PM UTC 24 Aug 29 04:03:33 PM UTC 24 2637431472 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1689652353 Aug 29 03:55:36 PM UTC 24 Aug 29 04:03:39 PM UTC 24 5008389720 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.2160165435 Aug 29 03:59:54 PM UTC 24 Aug 29 04:04:17 PM UTC 24 2312922830 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.3095867173 Aug 29 03:48:23 PM UTC 24 Aug 29 04:04:36 PM UTC 24 6022616256 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_idle.353893459 Aug 29 04:00:20 PM UTC 24 Aug 29 04:04:38 PM UTC 24 3388296410 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1016560128 Aug 29 03:54:39 PM UTC 24 Aug 29 04:04:55 PM UTC 24 6582806740 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.1480712405 Aug 29 04:01:04 PM UTC 24 Aug 29 04:05:10 PM UTC 24 2009356792 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.4166565039 Aug 29 03:54:05 PM UTC 24 Aug 29 04:05:20 PM UTC 24 3461169940 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc.3175375388 Aug 29 03:59:59 PM UTC 24 Aug 29 04:05:27 PM UTC 24 3357299112 ps
T887 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1419918264 Aug 29 03:59:51 PM UTC 24 Aug 29 04:05:35 PM UTC 24 3130768878 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.59715025 Aug 29 03:45:17 PM UTC 24 Aug 29 04:05:43 PM UTC 24 12536403329 ps
T888 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.378649439 Aug 29 04:00:17 PM UTC 24 Aug 29 04:06:03 PM UTC 24 3393604000 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.14377772 Aug 29 03:34:58 PM UTC 24 Aug 29 04:06:04 PM UTC 24 17173572160 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.1148785328 Aug 29 04:01:12 PM UTC 24 Aug 29 04:06:36 PM UTC 24 3551364051 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.1679952565 Aug 29 03:48:48 PM UTC 24 Aug 29 04:07:08 PM UTC 24 5489289136 ps
T889 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2156281307 Aug 29 03:44:13 PM UTC 24 Aug 29 04:08:24 PM UTC 24 15934064641 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.1387976740 Aug 29 04:03:50 PM UTC 24 Aug 29 04:08:54 PM UTC 24 2507434966 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.596293716 Aug 29 03:44:51 PM UTC 24 Aug 29 04:09:00 PM UTC 24 10506684641 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1223194753 Aug 29 04:00:20 PM UTC 24 Aug 29 04:09:53 PM UTC 24 3733076000 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2969515239 Aug 29 04:00:48 PM UTC 24 Aug 29 04:10:23 PM UTC 24 8914211723 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.610991903 Aug 29 03:54:04 PM UTC 24 Aug 29 04:11:41 PM UTC 24 4766308650 ps
T890 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1111457945 Aug 29 04:04:17 PM UTC 24 Aug 29 04:11:47 PM UTC 24 4048974088 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.902598009 Aug 29 04:01:45 PM UTC 24 Aug 29 04:11:48 PM UTC 24 5548347200 ps
T652 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.433293891 Aug 29 03:50:45 PM UTC 24 Aug 29 04:11:53 PM UTC 24 8274414104 ps
T891 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.3223632682 Aug 29 04:07:11 PM UTC 24 Aug 29 04:11:59 PM UTC 24 2781951810 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.4167605194 Aug 29 04:00:16 PM UTC 24 Aug 29 04:12:29 PM UTC 24 4287309109 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1843438491 Aug 29 04:01:15 PM UTC 24 Aug 29 04:12:53 PM UTC 24 8657067300 ps
T892 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.427169900 Aug 29 04:04:51 PM UTC 24 Aug 29 04:13:02 PM UTC 24 5179922876 ps
T893 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1807445870 Aug 29 04:01:05 PM UTC 24 Aug 29 04:13:12 PM UTC 24 6283441128 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.392872870 Aug 29 04:03:46 PM UTC 24 Aug 29 04:13:22 PM UTC 24 3751377336 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.4090515436 Aug 29 03:42:20 PM UTC 24 Aug 29 04:13:30 PM UTC 24 13110330450 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3349883346 Aug 29 03:53:07 PM UTC 24 Aug 29 04:14:06 PM UTC 24 11607658358 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1599587092 Aug 29 03:43:55 PM UTC 24 Aug 29 04:14:11 PM UTC 24 21131350899 ps
T894 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3821516019 Aug 29 04:04:17 PM UTC 24 Aug 29 04:14:30 PM UTC 24 5619294456 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.3785725432 Aug 29 04:01:11 PM UTC 24 Aug 29 04:14:48 PM UTC 24 7324247462 ps
T895 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.595311863 Aug 29 04:06:40 PM UTC 24 Aug 29 04:15:02 PM UTC 24 4556239040 ps
T896 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1580447393 Aug 29 04:07:15 PM UTC 24 Aug 29 04:15:05 PM UTC 24 3294555400 ps
T686 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.2518988632 Aug 29 04:07:16 PM UTC 24 Aug 29 04:15:23 PM UTC 24 4160435922 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2582397159 Aug 29 04:06:15 PM UTC 24 Aug 29 04:16:01 PM UTC 24 6585767831 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.2390510873 Aug 29 04:03:50 PM UTC 24 Aug 29 04:16:02 PM UTC 24 4650593468 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3271242305 Aug 29 03:59:46 PM UTC 24 Aug 29 04:16:03 PM UTC 24 6147553331 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.1047620715 Aug 29 03:56:05 PM UTC 24 Aug 29 04:16:07 PM UTC 24 6556328040 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4294345177 Aug 29 04:10:27 PM UTC 24 Aug 29 04:16:48 PM UTC 24 7098768500 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3578112165 Aug 29 04:07:14 PM UTC 24 Aug 29 04:16:49 PM UTC 24 4049550100 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3106364257 Aug 29 04:06:16 PM UTC 24 Aug 29 04:16:51 PM UTC 24 5269618260 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.1348786942 Aug 29 04:14:40 PM UTC 24 Aug 29 04:17:13 PM UTC 24 2891955275 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2028658096 Aug 29 04:06:54 PM UTC 24 Aug 29 04:17:30 PM UTC 24 4877077666 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1390906240 Aug 29 04:07:18 PM UTC 24 Aug 29 04:17:36 PM UTC 24 5268657126 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4212427158 Aug 29 04:07:13 PM UTC 24 Aug 29 04:18:36 PM UTC 24 5438331640 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1277883705 Aug 29 04:07:07 PM UTC 24 Aug 29 04:18:46 PM UTC 24 4291213380 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1752386258 Aug 29 04:00:00 PM UTC 24 Aug 29 04:18:55 PM UTC 24 6873934720 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.871830855 Aug 29 04:01:12 PM UTC 24 Aug 29 04:19:02 PM UTC 24 9420532401 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.538963901 Aug 29 04:14:44 PM UTC 24 Aug 29 04:19:10 PM UTC 24 3328492640 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3941627631 Aug 29 04:06:46 PM UTC 24 Aug 29 04:19:11 PM UTC 24 4110932482 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.942094454 Aug 29 04:09:39 PM UTC 24 Aug 29 04:19:35 PM UTC 24 3899456214 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.2281239680 Aug 29 04:13:40 PM UTC 24 Aug 29 04:19:57 PM UTC 24 4454306469 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1657566693 Aug 29 04:15:20 PM UTC 24 Aug 29 04:20:15 PM UTC 24 3093182029 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.76894523 Aug 29 04:13:08 PM UTC 24 Aug 29 04:20:44 PM UTC 24 3711152328 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.1318692479 Aug 29 03:46:46 PM UTC 24 Aug 29 04:20:52 PM UTC 24 23402261610 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1337129576 Aug 29 04:13:41 PM UTC 24 Aug 29 04:20:54 PM UTC 24 4883973738 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.976399901 Aug 29 04:17:05 PM UTC 24 Aug 29 04:20:57 PM UTC 24 2540124209 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.3319290350 Aug 29 03:32:28 PM UTC 24 Aug 29 04:21:13 PM UTC 24 12483612110 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.1273399209 Aug 29 03:55:52 PM UTC 24 Aug 29 04:21:20 PM UTC 24 7172845790 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.3226894043 Aug 29 04:13:04 PM UTC 24 Aug 29 04:21:22 PM UTC 24 6490692344 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.1936267556 Aug 29 04:15:58 PM UTC 24 Aug 29 04:21:51 PM UTC 24 3599454721 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3968415761 Aug 29 03:53:12 PM UTC 24 Aug 29 04:22:03 PM UTC 24 7989826794 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.1133767699 Aug 29 04:15:59 PM UTC 24 Aug 29 04:22:10 PM UTC 24 3194034136 ps
T897 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.441272283 Aug 29 04:17:56 PM UTC 24 Aug 29 04:22:22 PM UTC 24 2504127752 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.413992589 Aug 29 04:13:45 PM UTC 24 Aug 29 04:22:28 PM UTC 24 5979870420 ps
T898 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.664623068 Aug 29 04:18:34 PM UTC 24 Aug 29 04:23:16 PM UTC 24 3269567874 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1516988018 Aug 29 03:41:48 PM UTC 24 Aug 29 04:23:18 PM UTC 24 30637141152 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.1964228426 Aug 29 04:13:55 PM UTC 24 Aug 29 04:23:19 PM UTC 24 6537865004 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.3035571146 Aug 29 04:02:50 PM UTC 24 Aug 29 04:23:21 PM UTC 24 6420772550 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.938201244 Aug 29 04:13:24 PM UTC 24 Aug 29 04:23:22 PM UTC 24 5578941640 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2220388196 Aug 29 04:18:29 PM UTC 24 Aug 29 04:23:28 PM UTC 24 3557731080 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.1242923885 Aug 29 04:13:55 PM UTC 24 Aug 29 04:23:29 PM UTC 24 5991354501 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2875081167 Aug 29 04:13:45 PM UTC 24 Aug 29 04:23:52 PM UTC 24 5553716531 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3657809085 Aug 29 03:52:55 PM UTC 24 Aug 29 04:23:54 PM UTC 24 8354863464 ps
T687 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.2711323791 Aug 29 04:09:39 PM UTC 24 Aug 29 04:24:36 PM UTC 24 6776118520 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_peri.428463229 Aug 29 04:04:11 PM UTC 24 Aug 29 04:24:45 PM UTC 24 10351915656 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.2728888008 Aug 29 04:00:02 PM UTC 24 Aug 29 04:25:55 PM UTC 24 8833857760 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.751527171 Aug 29 04:20:05 PM UTC 24 Aug 29 04:26:06 PM UTC 24 4399347808 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_scrambling_smoketest.3748023585 Aug 29 04:22:52 PM UTC 24 Aug 29 04:26:12 PM UTC 24 2977762304 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation.99661090 Aug 29 03:59:50 PM UTC 24 Aug 29 04:26:59 PM UTC 24 8176227716 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3851614270 Aug 29 04:17:06 PM UTC 24 Aug 29 04:27:00 PM UTC 24 5052205738 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_crash_alert.2290940632 Aug 29 04:15:59 PM UTC 24 Aug 29 04:27:02 PM UTC 24 5911584650 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2666909257 Aug 29 04:18:37 PM UTC 24 Aug 29 04:27:03 PM UTC 24 5532112305 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.522966057 Aug 29 04:18:34 PM UTC 24 Aug 29 04:28:19 PM UTC 24 4569791022 ps
T899 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.2449000117 Aug 29 03:59:51 PM UTC 24 Aug 29 04:28:42 PM UTC 24 7605204440 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2455288460 Aug 29 03:59:24 PM UTC 24 Aug 29 04:31:37 PM UTC 24 9680915960 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.1938001315 Aug 29 04:08:44 PM UTC 24 Aug 29 04:33:30 PM UTC 24 13497966352 ps
T900 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.717601481 Aug 29 04:17:04 PM UTC 24 Aug 29 04:34:04 PM UTC 24 7771587302 ps
T901 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_sw_mode.3003144934 Aug 29 03:54:38 PM UTC 24 Aug 29 04:37:53 PM UTC 24 10329204916 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.2077737101 Aug 29 03:59:35 PM UTC 24 Aug 29 04:38:10 PM UTC 24 12404558020 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.575463677 Aug 29 04:13:13 PM UTC 24 Aug 29 04:38:18 PM UTC 24 20626657156 ps
T902 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1486562152 Aug 29 04:20:55 PM UTC 24 Aug 29 04:39:48 PM UTC 24 5368805960 ps
T663 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3292198003 Aug 29 04:02:24 PM UTC 24 Aug 29 04:42:22 PM UTC 24 25970011894 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1072152022 Aug 29 04:18:24 PM UTC 24 Aug 29 04:43:53 PM UTC 24 10273547435 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.433301916 Aug 29 03:46:43 PM UTC 24 Aug 29 04:43:54 PM UTC 24 21121132927 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.4072822531 Aug 29 04:07:28 PM UTC 24 Aug 29 04:44:58 PM UTC 24 19138431957 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2611040239 Aug 29 04:13:08 PM UTC 24 Aug 29 04:46:28 PM UTC 24 21639392928 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.2507037548 Aug 29 04:24:50 PM UTC 24 Aug 29 04:51:18 PM UTC 24 5693432792 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.2739977051 Aug 29 04:18:27 PM UTC 24 Aug 29 04:54:40 PM UTC 24 23284494089 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.2498691329 Aug 29 04:51:54 PM UTC 24 Aug 29 04:54:53 PM UTC 24 2414057079 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_stream.2377308923 Aug 29 03:34:09 PM UTC 24 Aug 29 04:55:46 PM UTC 24 19061178672 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_raw_unlock.3032726259 Aug 29 04:55:27 PM UTC 24 Aug 29 04:59:12 PM UTC 24 5779139206 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2975984370 Aug 29 03:49:07 PM UTC 24 Aug 29 04:59:37 PM UTC 24 18240409691 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_keymgr_functest.2029815309 Aug 29 04:56:20 PM UTC 24 Aug 29 05:04:03 PM UTC 24 5241441492 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.213822307 Aug 29 03:48:22 PM UTC 24 Aug 29 05:04:28 PM UTC 24 16405719672 ps
T903 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_smoketest.2405461937 Aug 29 04:59:46 PM UTC 24 Aug 29 05:04:47 PM UTC 24 2887237426 ps
T904 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_smoketest.1242070612 Aug 29 05:00:10 PM UTC 24 Aug 29 05:06:55 PM UTC 24 2638639072 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.3653382543 Aug 29 03:59:52 PM UTC 24 Aug 29 05:08:06 PM UTC 24 14170838832 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.1925534602 Aug 29 03:35:53 PM UTC 24 Aug 29 05:09:00 PM UTC 24 43911750454 ps
T905 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_smoketest.4072027242 Aug 29 05:04:37 PM UTC 24 Aug 29 05:09:04 PM UTC 24 2839885498 ps
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T907 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_smoketest.2136317566 Aug 29 05:05:18 PM UTC 24 Aug 29 05:11:09 PM UTC 24 2774049452 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.1723141062 Aug 29 04:34:34 PM UTC 24 Aug 29 05:11:43 PM UTC 24 12059521983 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio_smoketest.1647374659 Aug 29 05:07:26 PM UTC 24 Aug 29 05:12:12 PM UTC 24 2916635507 ps
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