Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	144654	1			T94	11		T95	5		T96	6
values[2]	11071	1			T241	1		T438	3		T453	2
values[3]	4592	1			T454	6		T615	1		T462	5
values[4]	2708	1			T454	4		T462	7		T502	3
values[5]	1710	1			T454	10		T462	10		T502	2
values[6]	1091	1			T454	6		T462	6		T502	5
values[7]	819	1			T454	6		T462	3		T799	5
values[8]	625	1			T454	3		T462	13		T799	4
values[9]	462	1			T454	8		T462	8		T797	2
values[10]	380	1			T454	16		T462	6		T797	4
values[11]	343	1			T454	12		T462	9		T797	3
values[12]	355	1			T454	6		T462	7		T797	5
values[13]	299	1			T454	5		T462	6		T797	5
values[14]	321	1			T454	5		T462	3		T797	7
values[15]	288	1			T454	4		T462	9		T797	1
values[16]	304	1			T454	11		T462	4		T797	1
values[17]	342	1			T454	6		T462	5		T797	4
values[18]	288	1			T454	3		T462	4		T797	5
values[19]	332	1			T454	6		T462	6		T797	6
values[20]	306	1			T454	9		T462	4		T797	1
values[21]	276	1			T454	7		T462	13		T646	3
values[22]	270	1			T454	10		T462	24		T646	7
values[23]	294	1			T454	15		T462	5		T646	11
values[24]	302	1			T454	4		T462	12		T646	11
values[25]	309	1			T454	16		T462	5		T646	8
values[26]	348	1			T454	15		T462	7		T646	3
values[27]	293	1			T454	3		T462	5		T646	4
values[28]	247	1			T454	4		T462	5		T646	4
values[29]	226	1			T454	2		T462	5		T646	5
values[30]	273	1			T454	3		T462	9		T646	4
values[31]	271	1			T454	7		T462	3		T646	7
values[32]	317	1			T454	3		T462	12		T646	26
values[33]	289	1			T454	14		T462	13		T646	9
values[34]	317	1			T454	24		T462	12		T646	6
values[35]	299	1			T454	6		T462	4		T646	6
values[36]	287	1			T454	16		T462	5		T646	7
values[37]	285	1			T454	7		T462	3		T646	5
values[38]	278	1			T454	24		T462	7		T646	4
values[39]	258	1			T454	6		T462	3		T646	9
values[40]	286	1			T454	2		T462	6		T646	4
values[41]	265	1			T454	4		T462	6		T646	9
values[42]	282	1			T454	5		T462	3		T646	9
values[43]	285	1			T454	12		T462	4		T646	6
values[44]	277	1			T454	5		T462	8		T646	8
values[45]	238	1			T454	8		T462	4		T646	4
values[46]	248	1			T454	4		T462	26		T646	5
values[47]	278	1			T454	5		T462	22		T646	3
values[48]	268	1			T454	19		T462	7		T646	7
values[49]	293	1			T454	7		T462	10		T646	11
values[50]	216	1			T454	5		T462	3		T646	4
values[51]	263	1			T454	6		T462	6		T646	9
values[52]	240	1			T454	6		T462	4		T646	13
values[53]	274	1			T454	4		T462	3		T646	6
values[54]	310	1			T454	9		T462	4		T646	14
values[55]	246	1			T454	6		T462	8		T831	2
values[56]	239	1			T454	9		T462	7		T831	2
values[57]	208	1			T454	5		T462	6		T831	4
values[58]	221	1			T454	17		T462	9		T831	1
values[59]	163	1			T454	8		T462	6		T831	1
values[60]	193	1			T454	9		T462	10		T831	2
values[61]	187	1			T454	10		T462	4		T831	1
values[62]	182	1			T454	12		T462	6		T610	3
values[63]	177	1			T454	9		T462	10		T610	3
values[64]	141	1			T454	3		T462	4		T610	2
values[65]	131	1			T454	4		T462	7		T610	2
values[66]	144	1			T454	8		T462	3		T610	1
values[67]	163	1			T454	5		T462	11		T610	1
values[68]	129	1			T454	4		T462	5		T610	2
values[69]	142	1			T454	5		T462	22		T610	4
values[70]	146	1			T454	5		T462	12		T610	1
values[71]	129	1			T454	8		T462	4		T610	2
values[72]	118	1			T454	6		T462	5		T610	1
values[73]	126	1			T454	3		T610	2		T495	13
values[74]	117	1			T454	8		T610	2		T495	11
values[75]	107	1			T454	5		T610	1		T495	5
values[76]	93	1			T454	8		T610	3		T495	6
values[77]	84	1			T454	3		T610	4		T495	7
values[78]	74	1			T610	2		T532	1		T850	1
values[79]	85	1			T610	1		T532	1		T850	1
values[80]	89	1			T610	3		T532	1		T850	1
values[81]	73	1			T610	2		T532	1		T850	1
values[82]	50	1			T610	3		T532	1		T850	1
values[83]	85	1			T610	5		T532	1		T850	1
values[84]	85	1			T610	6		T532	1		T850	1
values[85]	70	1			T610	8		T532	1		T850	1
values[86]	72	1			T610	3		T532	1		T850	1
values[87]	83	1			T610	8		T532	1		T850	1
values[88]	71	1			T610	11		T532	1		T850	1
values[89]	96	1			T610	15		T532	1		T850	1
values[90]	71	1			T610	10		T532	1		T850	1
values[91]	70	1			T610	1		T532	1		T850	1
values[92]	93	1			T610	4		T532	1		T850	1
values[93]	73	1			T610	3		T532	1		T850	1
values[94]	100	1			T610	2		T532	1		T850	1
values[95]	98	1			T610	3		T532	1		T850	1
values[96]	72	1			T610	5		T532	2		T850	1
values[97]	70	1			T610	5		T532	4		T850	1
values[98]	73	1			T610	11		T532	2		T850	1
values[99]	72	1			T610	3		T532	2		T850	1
values[100]	57	1			T610	5		T532	2		T850	1
values[101]	47	1			T610	5		T532	3		T850	1
values[102]	55	1			T610	2		T532	4		T850	1
values[103]	62	1			T610	3		T532	2		T850	1
values[104]	57	1			T610	2		T532	5		T850	1
values[105]	50	1			T610	5		T532	3		T850	1
values[106]	65	1			T610	7		T532	4		T850	1
values[107]	61	1			T610	8		T532	1		T850	1
values[108]	69	1			T610	3		T532	3		T850	1
values[109]	52	1			T610	2		T532	4		T850	1
values[110]	66	1			T610	6		T532	3		T850	1
values[111]	63	1			T610	3		T532	1		T850	1
values[112]	52	1			T610	6		T532	4		T850	1
values[113]	67	1			T610	7		T532	2		T850	1
values[114]	59	1			T610	5		T532	2		T850	1
values[115]	42	1			T610	3		T532	1		T850	1
values[116]	70	1			T610	5		T532	4		T850	1
values[117]	45	1			T610	2		T532	3		T850	1
values[118]	47	1			T610	4		T532	1		T850	1
values[119]	59	1			T610	4		T532	1		T850	1
values[120]	70	1			T610	4		T532	2		T850	1
values[121]	45	1			T610	5		T532	1		T850	1
values[122]	48	1			T610	3		T532	1		T850	5
values[123]	46	1			T610	6		T532	2		T850	1
values[124]	42	1			T610	6		T532	2		T850	1
values[125]	62	1			T610	8		T532	5		T850	1
values[126]	85	1			T610	12		T532	1		T850	5
values[127]	588	1			T610	11		T532	30		T850	26
values[128]	5072	1			T610	6		T532	301		T850	247