Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	477	1			T558	1		T441	1		T550	2
all_values[1]	486	1			T558	1		T441	5		T550	3
all_values[2]	494	1			T441	1		T550	3		T647	1
all_values[3]	457	1			T441	1		T550	3		T502	1
all_values[4]	477	1			T558	1		T441	2		T550	3
all_values[5]	472	1			T558	1		T441	1		T647	1
all_values[6]	470	1			T558	1		T550	5		T582	2
all_values[7]	498	1			T558	1		T441	1		T550	2
all_values[8]	449	1			T441	3		T550	5		T502	1
all_values[9]	481	1			T454	1		T558	2		T441	3
all_values[10]	500	1			T558	2		T441	2		T550	1
all_values[11]	475	1			T558	5		T441	3		T550	5
all_values[12]	503	1			T558	1		T441	1		T550	5
all_values[13]	470	1			T558	1		T441	2		T550	4
all_values[14]	446	1			T570	1		T441	3		T550	1
all_values[15]	510	1			T558	2		T550	3		T647	2
all_values[16]	515	1			T550	1		T502	2		T581	1
all_values[17]	494	1			T441	2		T550	2		T582	1
all_values[18]	453	1			T441	3		T550	7		T582	1
all_values[19]	511	1			T454	1		T441	2		T550	2
all_values[20]	486	1			T558	1		T550	1		T582	1
all_values[21]	503	1			T689	1		T441	2		T550	2
all_values[22]	477	1			T441	1		T550	5		T462	3
all_values[23]	493	1			T550	3		T470	1		T502	4
all_values[24]	552	1			T570	1		T558	3		T441	1
all_values[25]	494	1			T558	1		T441	2		T550	4
all_values[26]	491	1			T558	1		T441	1		T550	4
all_values[27]	497	1			T441	3		T550	3		T582	1
all_values[28]	459	1			T441	1		T550	8		T502	3
all_values[29]	445	1			T558	1		T441	3		T470	2
all_values[30]	475	1			T558	1		T441	2		T550	2
all_values[31]	537	1			T441	5		T550	1		T647	1
all_values[32]	486	1			T558	1		T441	2		T550	1
all_values[33]	500	1			T441	4		T550	3		T582	1
all_values[34]	541	1			T441	4		T550	2		T571	1
all_values[35]	484	1			T689	2		T441	1		T550	4
all_values[36]	488	1			T441	3		T550	2		T502	3
all_values[37]	495	1			T558	2		T441	3		T550	2
all_values[38]	478	1			T558	3		T441	2		T550	2
all_values[39]	474	1			T558	1		T441	1		T550	5
all_values[40]	486	1			T558	1		T462	1		T502	2
all_values[41]	492	1			T570	1		T441	3		T550	2
all_values[42]	490	1			T558	1		T550	8		T582	1
all_values[43]	503	1			T441	2		T550	2		T571	1
all_values[44]	508	1			T441	3		T550	7		T582	2
all_values[45]	497	1			T454	1		T550	2		T462	1
all_values[46]	497	1			T689	1		T441	2		T550	3
all_values[47]	512	1			T558	1		T441	1		T550	2
all_values[48]	472	1			T441	1		T550	2		T582	2
all_values[49]	526	1			T441	2		T550	4		T582	1