Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3531	1			T456	2		T555	1		T548	1
all_values[1]	3450	1			T98	1		T456	2		T548	2
all_values[2]	3481	1			T98	1		T456	3		T555	1
all_values[3]	3383	1			T98	1		T555	1		T548	1
all_values[4]	3535	1			T98	1		T456	1		T548	2
all_values[5]	3420	1			T98	1		T456	1		T558	15
all_values[6]	3365	1			T548	3		T558	11		T441	13
all_values[7]	3546	1			T98	1		T548	2		T558	16
all_values[8]	3521	1			T555	2		T548	3		T558	11
all_values[9]	3459	1			T548	1		T558	11		T441	18
all_values[10]	3445	1			T456	2		T548	1		T558	10
all_values[11]	3489	1			T456	2		T555	1		T548	2
all_values[12]	3520	1			T456	1		T548	2		T558	16
all_values[13]	3447	1			T548	3		T558	8		T441	13
all_values[14]	3481	1			T456	2		T548	2		T558	14
all_values[15]	3416	1			T456	1		T548	1		T558	9
all_values[16]	3505	1			T558	12		T441	14		T549	2
all_values[17]	3506	1			T548	1		T558	14		T441	15
all_values[18]	3456	1			T98	2		T456	3		T548	4
all_values[19]	3526	1			T555	1		T548	1		T558	13
all_values[20]	3396	1			T555	1		T548	2		T558	15
all_values[21]	3486	1			T98	2		T456	1		T555	1
all_values[22]	3480	1			T456	1		T548	2		T558	8
all_values[23]	3429	1			T456	1		T548	3		T558	12
all_values[24]	3530	1			T98	1		T548	1		T558	19
all_values[25]	3507	1			T456	1		T548	1		T558	10
all_values[26]	3596	1			T456	1		T558	12		T441	12
all_values[27]	3571	1			T548	3		T558	11		T441	17
all_values[28]	3411	1			T98	1		T548	1		T558	8
all_values[29]	3481	1			T555	2		T558	19		T441	20
all_values[30]	3488	1			T456	1		T548	3		T558	6
all_values[31]	3373	1			T456	3		T555	2		T558	4
all_values[32]	3442	1			T456	2		T558	8		T441	11
all_values[33]	3552	1			T456	1		T555	1		T548	1
all_values[34]	3420	1			T98	1		T456	1		T555	1
all_values[35]	3641	1			T456	2		T548	3		T558	16
all_values[36]	3355	1			T456	1		T548	2		T558	15
all_values[37]	3497	1			T98	1		T548	1		T558	16
all_values[38]	3407	1			T548	1		T558	5		T441	12
all_values[39]	3449	1			T456	1		T548	1		T558	15
all_values[40]	3475	1			T558	10		T441	10		T549	5
all_values[41]	3449	1			T98	1		T548	2		T558	7
all_values[42]	3483	1			T456	2		T555	1		T558	12
all_values[43]	3417	1			T456	2		T548	1		T558	13
all_values[44]	3512	1			T98	1		T456	2		T558	13
all_values[45]	3638	1			T456	1		T555	2		T548	1
all_values[46]	3544	1			T456	1		T555	2		T558	11
all_values[47]	3399	1			T548	2		T558	19		T441	6
all_values[48]	3521	1			T456	2		T548	1		T558	10
all_values[49]	3447	1			T558	7		T441	6		T549	2
all_values[50]	3456	1			T456	1		T548	2		T558	11
all_values[51]	3457	1			T456	1		T555	1		T558	11
all_values[52]	3456	1			T98	1		T456	2		T558	15
all_values[53]	3477	1			T555	1		T548	5		T558	9
all_values[54]	3463	1			T456	1		T555	2		T558	15
all_values[55]	3521	1			T548	1		T558	9		T441	17
all_values[56]	3425	1			T555	2		T558	15		T441	8
all_values[57]	3519	1			T456	1		T548	2		T558	14
all_values[58]	3460	1			T456	2		T558	14		T441	14
all_values[59]	3590	1			T456	1		T548	1		T558	14
all_values[60]	3612	1			T98	1		T456	1		T548	2
all_values[61]	3486	1			T548	1		T558	14		T441	16
all_values[62]	3403	1			T456	2		T555	2		T548	1
all_values[63]	3516	1			T558	9		T441	15		T549	6