Go
back
73 // Glue logic between rv_plic_reg_top and others
74 1/1 assign cc_id = irq_id_o;
Tests: T2 T5 T6
75
76 always_comb begin
77 1/1 claim = '0;
Tests: T2 T5 T6
78 1/1 for (int i = 0 ; i < NumTarget ; i++) begin
Tests: T2 T5 T6
79 2/2 if (claim_re[i]) claim[claim_id[i]] = 1'b1;
Tests: T2 T5 T6 | T2 T5 T6
MISSING_ELSE
80 end
81 end
82 always_comb begin
83 1/1 complete = '0;
Tests: T2 T5 T8
84 1/1 for (int i = 0 ; i < NumTarget ; i++) begin
Tests: T2 T5 T8
85 2/2 if (complete_we[i]) complete[complete_id[i]] = 1'b1;
Tests: T2 T5 T8 | T2 T5 T6
MISSING_ELSE
86 end
87 end
88
89 //`ASSERT_PULSE(claimPulse, claim_re[i])
90 //`ASSERT_PULSE(completePulse, complete_we[i])
91
92 `ASSERT(onehot0Claim, $onehot0(claim_re))
93
94 `ASSERT(onehot0Complete, $onehot0(complete_we))
95
96 //////////////
97 // Priority //
98 //////////////
99 1/1 assign prio[0] = reg2hw.prio0.q;
Tests: T280 T281 T322
100 1/1 assign prio[1] = reg2hw.prio1.q;
Tests: T127 T128 T280
101 1/1 assign prio[2] = reg2hw.prio2.q;
Tests: T127 T128 T280
102 1/1 assign prio[3] = reg2hw.prio3.q;
Tests: T127 T128 T280
103 1/1 assign prio[4] = reg2hw.prio4.q;
Tests: T127 T128 T280
104 1/1 assign prio[5] = reg2hw.prio5.q;
Tests: T127 T128 T280
105 1/1 assign prio[6] = reg2hw.prio6.q;
Tests: T127 T128 T280
106 1/1 assign prio[7] = reg2hw.prio7.q;
Tests: T127 T128 T280
107 1/1 assign prio[8] = reg2hw.prio8.q;
Tests: T127 T128 T280
108 1/1 assign prio[9] = reg2hw.prio9.q;
Tests: T127 T128 T280
109 1/1 assign prio[10] = reg2hw.prio10.q;
Tests: T129 T280 T120
110 1/1 assign prio[11] = reg2hw.prio11.q;
Tests: T129 T280 T120
111 1/1 assign prio[12] = reg2hw.prio12.q;
Tests: T129 T280 T120
112 1/1 assign prio[13] = reg2hw.prio13.q;
Tests: T129 T280 T120
113 1/1 assign prio[14] = reg2hw.prio14.q;
Tests: T129 T280 T120
114 1/1 assign prio[15] = reg2hw.prio15.q;
Tests: T129 T280 T120
115 1/1 assign prio[16] = reg2hw.prio16.q;
Tests: T129 T280 T120
116 1/1 assign prio[17] = reg2hw.prio17.q;
Tests: T129 T280 T120
117 1/1 assign prio[18] = reg2hw.prio18.q;
Tests: T129 T280 T120
118 1/1 assign prio[19] = reg2hw.prio19.q;
Tests: T64 T65 T280
119 1/1 assign prio[20] = reg2hw.prio20.q;
Tests: T64 T65 T280
120 1/1 assign prio[21] = reg2hw.prio21.q;
Tests: T64 T65 T280
121 1/1 assign prio[22] = reg2hw.prio22.q;
Tests: T64 T65 T280
122 1/1 assign prio[23] = reg2hw.prio23.q;
Tests: T64 T65 T280
123 1/1 assign prio[24] = reg2hw.prio24.q;
Tests: T64 T65 T280
124 1/1 assign prio[25] = reg2hw.prio25.q;
Tests: T64 T65 T280
125 1/1 assign prio[26] = reg2hw.prio26.q;
Tests: T64 T65 T280
126 1/1 assign prio[27] = reg2hw.prio27.q;
Tests: T64 T65 T280
127 1/1 assign prio[28] = reg2hw.prio28.q;
Tests: T29 T66 T280
128 1/1 assign prio[29] = reg2hw.prio29.q;
Tests: T29 T66 T280
129 1/1 assign prio[30] = reg2hw.prio30.q;
Tests: T29 T66 T280
130 1/1 assign prio[31] = reg2hw.prio31.q;
Tests: T29 T66 T280
131 1/1 assign prio[32] = reg2hw.prio32.q;
Tests: T29 T66 T280
132 1/1 assign prio[33] = reg2hw.prio33.q;
Tests: T29 T66 T280
133 1/1 assign prio[34] = reg2hw.prio34.q;
Tests: T29 T66 T280
134 1/1 assign prio[35] = reg2hw.prio35.q;
Tests: T29 T66 T280
135 1/1 assign prio[36] = reg2hw.prio36.q;
Tests: T29 T66 T280
136 1/1 assign prio[37] = reg2hw.prio37.q;
Tests: T30 T280 T120
137 1/1 assign prio[38] = reg2hw.prio38.q;
Tests: T30 T280 T120
138 1/1 assign prio[39] = reg2hw.prio39.q;
Tests: T30 T280 T120
139 1/1 assign prio[40] = reg2hw.prio40.q;
Tests: T30 T280 T120
140 1/1 assign prio[41] = reg2hw.prio41.q;
Tests: T30 T280 T120
141 1/1 assign prio[42] = reg2hw.prio42.q;
Tests: T30 T280 T120
142 1/1 assign prio[43] = reg2hw.prio43.q;
Tests: T30 T280 T120
143 1/1 assign prio[44] = reg2hw.prio44.q;
Tests: T30 T280 T120
144 1/1 assign prio[45] = reg2hw.prio45.q;
Tests: T30 T280 T120
145 1/1 assign prio[46] = reg2hw.prio46.q;
Tests: T30 T280 T120
146 1/1 assign prio[47] = reg2hw.prio47.q;
Tests: T30 T280 T120
147 1/1 assign prio[48] = reg2hw.prio48.q;
Tests: T30 T280 T120
148 1/1 assign prio[49] = reg2hw.prio49.q;
Tests: T30 T280 T120
149 1/1 assign prio[50] = reg2hw.prio50.q;
Tests: T30 T280 T120
150 1/1 assign prio[51] = reg2hw.prio51.q;
Tests: T30 T280 T120
151 1/1 assign prio[52] = reg2hw.prio52.q;
Tests: T30 T280 T120
152 1/1 assign prio[53] = reg2hw.prio53.q;
Tests: T30 T280 T120
153 1/1 assign prio[54] = reg2hw.prio54.q;
Tests: T30 T280 T120
154 1/1 assign prio[55] = reg2hw.prio55.q;
Tests: T30 T280 T120
155 1/1 assign prio[56] = reg2hw.prio56.q;
Tests: T30 T280 T120
156 1/1 assign prio[57] = reg2hw.prio57.q;
Tests: T30 T280 T120
157 1/1 assign prio[58] = reg2hw.prio58.q;
Tests: T30 T280 T120
158 1/1 assign prio[59] = reg2hw.prio59.q;
Tests: T30 T280 T120
159 1/1 assign prio[60] = reg2hw.prio60.q;
Tests: T30 T280 T120
160 1/1 assign prio[61] = reg2hw.prio61.q;
Tests: T30 T280 T120
161 1/1 assign prio[62] = reg2hw.prio62.q;
Tests: T30 T280 T120
162 1/1 assign prio[63] = reg2hw.prio63.q;
Tests: T30 T280 T120
163 1/1 assign prio[64] = reg2hw.prio64.q;
Tests: T30 T280 T120
164 1/1 assign prio[65] = reg2hw.prio65.q;
Tests: T30 T280 T120
165 1/1 assign prio[66] = reg2hw.prio66.q;
Tests: T30 T280 T120
166 1/1 assign prio[67] = reg2hw.prio67.q;
Tests: T30 T280 T120
167 1/1 assign prio[68] = reg2hw.prio68.q;
Tests: T30 T280 T120
168 1/1 assign prio[69] = reg2hw.prio69.q;
Tests: T14 T30 T11
169 1/1 assign prio[70] = reg2hw.prio70.q;
Tests: T14 T280 T120
170 1/1 assign prio[71] = reg2hw.prio71.q;
Tests: T14 T280 T120
171 1/1 assign prio[72] = reg2hw.prio72.q;
Tests: T14 T11 T12
172 1/1 assign prio[73] = reg2hw.prio73.q;
Tests: T14 T11 T12
173 1/1 assign prio[74] = reg2hw.prio74.q;
Tests: T14 T280 T120
174 1/1 assign prio[75] = reg2hw.prio75.q;
Tests: T280 T120 T323
175 1/1 assign prio[76] = reg2hw.prio76.q;
Tests: T280 T120 T323
176 1/1 assign prio[77] = reg2hw.prio77.q;
Tests: T60 T280 T120
177 1/1 assign prio[78] = reg2hw.prio78.q;
Tests: T60 T280 T120
178 1/1 assign prio[79] = reg2hw.prio79.q;
Tests: T280 T120 T323
179 1/1 assign prio[80] = reg2hw.prio80.q;
Tests: T60 T280 T120
180 1/1 assign prio[81] = reg2hw.prio81.q;
Tests: T60 T280 T120
181 1/1 assign prio[82] = reg2hw.prio82.q;
Tests: T60 T280 T120
182 1/1 assign prio[83] = reg2hw.prio83.q;
Tests: T60 T280 T120
183 1/1 assign prio[84] = reg2hw.prio84.q;
Tests: T60 T280 T120
184 1/1 assign prio[85] = reg2hw.prio85.q;
Tests: T280 T120 T323
185 1/1 assign prio[86] = reg2hw.prio86.q;
Tests: T60 T280 T120
186 1/1 assign prio[87] = reg2hw.prio87.q;
Tests: T280 T120 T323
187 1/1 assign prio[88] = reg2hw.prio88.q;
Tests: T280 T120 T323
188 1/1 assign prio[89] = reg2hw.prio89.q;
Tests: T280 T120 T323
189 1/1 assign prio[90] = reg2hw.prio90.q;
Tests: T280 T120 T323
190 1/1 assign prio[91] = reg2hw.prio91.q;
Tests: T280 T120 T323
191 1/1 assign prio[92] = reg2hw.prio92.q;
Tests: T62 T280 T120
192 1/1 assign prio[93] = reg2hw.prio93.q;
Tests: T62 T280 T120
193 1/1 assign prio[94] = reg2hw.prio94.q;
Tests: T280 T120 T323
194 1/1 assign prio[95] = reg2hw.prio95.q;
Tests: T62 T280 T120
195 1/1 assign prio[96] = reg2hw.prio96.q;
Tests: T62 T280 T120
196 1/1 assign prio[97] = reg2hw.prio97.q;
Tests: T62 T280 T120
197 1/1 assign prio[98] = reg2hw.prio98.q;
Tests: T62 T280 T120
198 1/1 assign prio[99] = reg2hw.prio99.q;
Tests: T62 T280 T120
199 1/1 assign prio[100] = reg2hw.prio100.q;
Tests: T280 T120 T323
200 1/1 assign prio[101] = reg2hw.prio101.q;
Tests: T61 T62 T280
201 1/1 assign prio[102] = reg2hw.prio102.q;
Tests: T61 T280 T120
202 1/1 assign prio[103] = reg2hw.prio103.q;
Tests: T280 T120 T323
203 1/1 assign prio[104] = reg2hw.prio104.q;
Tests: T61 T280 T120
204 1/1 assign prio[105] = reg2hw.prio105.q;
Tests: T61 T280 T120
205 1/1 assign prio[106] = reg2hw.prio106.q;
Tests: T61 T280 T120
206 1/1 assign prio[107] = reg2hw.prio107.q;
Tests: T63 T280 T120
207 1/1 assign prio[108] = reg2hw.prio108.q;
Tests: T63 T280 T120
208 1/1 assign prio[109] = reg2hw.prio109.q;
Tests: T280 T120 T323
209 1/1 assign prio[110] = reg2hw.prio110.q;
Tests: T63 T280 T120
210 1/1 assign prio[111] = reg2hw.prio111.q;
Tests: T63 T280 T120
211 1/1 assign prio[112] = reg2hw.prio112.q;
Tests: T63 T280 T120
212 1/1 assign prio[113] = reg2hw.prio113.q;
Tests: T63 T280 T120
213 1/1 assign prio[114] = reg2hw.prio114.q;
Tests: T63 T280 T120
214 1/1 assign prio[115] = reg2hw.prio115.q;
Tests: T280 T120 T323
215 1/1 assign prio[116] = reg2hw.prio116.q;
Tests: T63 T280 T120
216 1/1 assign prio[117] = reg2hw.prio117.q;
Tests: T280 T120 T323
217 1/1 assign prio[118] = reg2hw.prio118.q;
Tests: T280 T120 T323
218 1/1 assign prio[119] = reg2hw.prio119.q;
Tests: T280 T120 T323
219 1/1 assign prio[120] = reg2hw.prio120.q;
Tests: T280 T120 T323
220 1/1 assign prio[121] = reg2hw.prio121.q;
Tests: T280 T120 T323
221 1/1 assign prio[122] = reg2hw.prio122.q;
Tests: T32 T280 T120
222 1/1 assign prio[123] = reg2hw.prio123.q;
Tests: T32 T280 T120
223 1/1 assign prio[124] = reg2hw.prio124.q;
Tests: T280 T120 T323
224 1/1 assign prio[125] = reg2hw.prio125.q;
Tests: T280 T120 T323
225 1/1 assign prio[126] = reg2hw.prio126.q;
Tests: T280 T120 T323
226 1/1 assign prio[127] = reg2hw.prio127.q;
Tests: T43 T44 T81
227 1/1 assign prio[128] = reg2hw.prio128.q;
Tests: T43 T44 T81
228 1/1 assign prio[129] = reg2hw.prio129.q;
Tests: T43 T44 T81
229 1/1 assign prio[130] = reg2hw.prio130.q;
Tests: T43 T44 T81
230 1/1 assign prio[131] = reg2hw.prio131.q;
Tests: T11 T12 T280
231 1/1 assign prio[132] = reg2hw.prio132.q;
Tests: T11 T12 T280
232 1/1 assign prio[133] = reg2hw.prio133.q;
Tests: T280 T120 T323
233 1/1 assign prio[134] = reg2hw.prio134.q;
Tests: T280 T120 T323
234 1/1 assign prio[135] = reg2hw.prio135.q;
Tests: T280 T120 T323
235 1/1 assign prio[136] = reg2hw.prio136.q;
Tests: T280 T120 T323
236 1/1 assign prio[137] = reg2hw.prio137.q;
Tests: T280 T120 T323
237 1/1 assign prio[138] = reg2hw.prio138.q;
Tests: T280 T120 T323
238 1/1 assign prio[139] = reg2hw.prio139.q;
Tests: T280 T120 T323
239 1/1 assign prio[140] = reg2hw.prio140.q;
Tests: T280 T120 T323
240 1/1 assign prio[141] = reg2hw.prio141.q;
Tests: T280 T120 T323
241 1/1 assign prio[142] = reg2hw.prio142.q;
Tests: T280 T120 T323
242 1/1 assign prio[143] = reg2hw.prio143.q;
Tests: T280 T120 T323
243 1/1 assign prio[144] = reg2hw.prio144.q;
Tests: T280 T120 T323
244 1/1 assign prio[145] = reg2hw.prio145.q;
Tests: T280 T120 T323
245 1/1 assign prio[146] = reg2hw.prio146.q;
Tests: T280 T120 T323
246 1/1 assign prio[147] = reg2hw.prio147.q;
Tests: T280 T120 T323
247 1/1 assign prio[148] = reg2hw.prio148.q;
Tests: T280 T120 T323
248 1/1 assign prio[149] = reg2hw.prio149.q;
Tests: T280 T120 T323
249 1/1 assign prio[150] = reg2hw.prio150.q;
Tests: T280 T120 T323
250 1/1 assign prio[151] = reg2hw.prio151.q;
Tests: T280 T120 T323
251 1/1 assign prio[152] = reg2hw.prio152.q;
Tests: T280 T120 T323
252 1/1 assign prio[153] = reg2hw.prio153.q;
Tests: T2 T8 T6
253 1/1 assign prio[154] = reg2hw.prio154.q;
Tests: T67 T280 T120
254 1/1 assign prio[155] = reg2hw.prio155.q;
Tests: T138 T280 T120
255 1/1 assign prio[156] = reg2hw.prio156.q;
Tests: T43 T44 T81
256 1/1 assign prio[157] = reg2hw.prio157.q;
Tests: T265 T43 T44
257 1/1 assign prio[158] = reg2hw.prio158.q;
Tests: T172 T280 T120
258 1/1 assign prio[159] = reg2hw.prio159.q;
Tests: T280 T120 T323
259 1/1 assign prio[160] = reg2hw.prio160.q;
Tests: T5 T307 T144
260 1/1 assign prio[161] = reg2hw.prio161.q;
Tests: T5 T307 T144
261 1/1 assign prio[162] = reg2hw.prio162.q;
Tests: T5 T307 T144
262 1/1 assign prio[163] = reg2hw.prio163.q;
Tests: T5 T307 T144
263 1/1 assign prio[164] = reg2hw.prio164.q;
Tests: T5 T307 T144
264 1/1 assign prio[165] = reg2hw.prio165.q;
Tests: T280 T120 T323
265 1/1 assign prio[166] = reg2hw.prio166.q;
Tests: T324 T325 T280
266 1/1 assign prio[167] = reg2hw.prio167.q;
Tests: T324 T325 T280
267 1/1 assign prio[168] = reg2hw.prio168.q;
Tests: T280 T120 T323
268 1/1 assign prio[169] = reg2hw.prio169.q;
Tests: T280 T120 T323
269 1/1 assign prio[170] = reg2hw.prio170.q;
Tests: T280 T120 T323
270 1/1 assign prio[171] = reg2hw.prio171.q;
Tests: T280 T120 T323
271 1/1 assign prio[172] = reg2hw.prio172.q;
Tests: T326 T280 T120
272 1/1 assign prio[173] = reg2hw.prio173.q;
Tests: T280 T120 T323
273 1/1 assign prio[174] = reg2hw.prio174.q;
Tests: T280 T120 T323
274 1/1 assign prio[175] = reg2hw.prio175.q;
Tests: T280 T120 T323
275 1/1 assign prio[176] = reg2hw.prio176.q;
Tests: T280 T120 T323
276 1/1 assign prio[177] = reg2hw.prio177.q;
Tests: T280 T120 T323
277 1/1 assign prio[178] = reg2hw.prio178.q;
Tests: T280 T120 T323
278 1/1 assign prio[179] = reg2hw.prio179.q;
Tests: T280 T120 T323
279 1/1 assign prio[180] = reg2hw.prio180.q;
Tests: T280 T120 T323
280 1/1 assign prio[181] = reg2hw.prio181.q;
Tests: T280 T120 T323
281 1/1 assign prio[182] = reg2hw.prio182.q;
Tests: T280 T120 T323
282 1/1 assign prio[183] = reg2hw.prio183.q;
Tests: T280 T120 T323
283 1/1 assign prio[184] = reg2hw.prio184.q;
Tests: T280 T120 T323
284 1/1 assign prio[185] = reg2hw.prio185.q;
Tests: T280 T120 T323
285
286 //////////////////////
287 // Interrupt Enable //
288 //////////////////////
289 for (genvar s = 0; s < 186; s++) begin : gen_ie0
290 186/186 assign ie[0][s] = reg2hw.ie0[s].q;
Tests: T280 T281 T322 | T127 T128 T280 | T127 T128 T280 | T127 T128 T280 | T127 T128 T280 | T127 T128 T280 | T127 T128 T280 | T127 T128 T280 | T127 T128 T280 | T127 T128 T280 | T129 T280 T120 | T129 T280 T120 | T129 T280 T120 | T129 T280 T120 | T129 T280 T120 | T129 T280 T120 | T129 T280 T120 | T129 T280 T120 | T129 T280 T120 | T64 T65 T280 | T64 T65 T280 | T64 T65 T280 | T64 T65 T280 | T64 T65 T280 | T64 T65 T280 | T64 T65 T280 | T64 T65 T280 | T64 T65 T280 | T29 T66 T280 | T29 T66 T280 | T29 T66 T280 | T29 T66 T280 | T29 T66 T280 | T29 T66 T280 | T29 T66 T280 | T29 T66 T280 | T29 T66 T280 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T30 T280 T120 | T14 T30 T11 | T14 T280 T120 | T14 T280 T120 | T14 T11 T12 | T14 T11 T12 | T14 T280 T120 | T280 T120 T323 | T280 T120 T323 | T60 T280 T120 | T60 T280 T120 | T280 T120 T323 | T60 T280 T120 | T60 T280 T120 | T60 T280 T120 | T60 T280 T120 | T60 T280 T120 | T280 T120 T323 | T60 T280 T120 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T62 T280 T120 | T62 T280 T120 | T280 T120 T323 | T62 T280 T120 | T62 T280 T120 | T62 T280 T120 | T62 T280 T120 | T62 T280 T120 | T280 T120 T323 | T61 T62 T280 | T61 T280 T120 | T280 T120 T323 | T61 T280 T120 | T61 T280 T120 | T61 T280 T120 | T63 T280 T120 | T63 T280 T120 | T280 T120 T323 | T63 T280 T120 | T63 T280 T120 | T63 T280 T120 | T63 T280 T120 | T63 T280 T120 | T280 T120 T323 | T63 T280 T120 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T32 T280 T120 | T32 T280 T120 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T43 T44 T81 | T43 T44 T81 | T43 T44 T81 | T43 T44 T81 | T11 T12 T280 | T11 T12 T280 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T2 T8 T6 | T67 T280 T120 | T138 T280 T120 | T43 T44 T81 | T265 T43 T44 | T172 T280 T120 | T280 T120 T323 | T5 T307 T144 | T5 T307 T144 | T5 T307 T144 | T5 T307 T144 | T5 T307 T144 | T280 T120 T323 | T324 T325 T280 | T324 T325 T280 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T326 T280 T120 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323 | T280 T120 T323
291 end
292
293 ////////////////////////
294 // THRESHOLD register //
295 ////////////////////////
296 0/1 ==> assign threshold[0] = reg2hw.threshold0.q;
297
298 /////////////////
299 // CC register //
300 /////////////////
301 1/1 assign claim_re[0] = reg2hw.cc0.re;
Tests: T2 T5 T6
302 1/1 assign claim_id[0] = irq_id_o[0];
Tests: T2 T5 T6
303 1/1 assign complete_we[0] = reg2hw.cc0.qe;
Tests: T2 T5 T6
304 1/1 assign complete_id[0] = reg2hw.cc0.q;
Tests: T2 T5 T8
305 1/1 assign hw2reg.cc0.d = cc_id[0];
Tests: T2 T5 T6
306
307 ///////////////////
308 // MSIP register //
309 ///////////////////
310 1/1 assign msip_o[0] = reg2hw.msip0.q;
Tests: T280 T69 T281
311
312 ////////
313 // IP //
314 ////////
315 for (genvar s = 0; s < 186; s++) begin : gen_ip
316 assign hw2reg.ip[s].de = 1'b1; // Always write
317 185/186 ==> assign hw2reg.ip[s].d = ip[s];
Tests: T127 T128 T323 | T127 T128 T323 | T127 T128 T323 | T127 T128 T323 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T127 T128 T323 | T129 T323 T130 | T129 T323 T130 | T129 T323 T130 | T129 T323 T130 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T129 T323 T130 | T64 T65 T323 | T64 T65 T323 | T64 T65 T323 | T64 T65 T323 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T64 T65 T323 | T29 T66 T323 | T29 T66 T323 | T29 T66 T323 | T29 T66 T323 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T29 T66 T323 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T30 T329 T41 | T11 T120 T223 | T120 T183 T184 | T120 T183 T184 | T120 T183 T184 | T120 T183 T184 | T14 T120 T49 | T120 T183 T184 | T120 T183 T184 | T60 T329 T122 | T60 T329 T122 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T60 T329 T122 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T62 T329 T137 | T62 T329 T137 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T61 T62 T329 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T63 T329 T123 | T63 T329 T123 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T63 T329 T123 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T32 T120 T183 | T120 T134 T183 | T119 T120 T121 | T120 T183 T184 | T120 T183 T184 | T44 T332 T333 | T334 T186 T100 | T329 T291 T297 | T43 T81 T185 | T120 T183 T184 | T120 T183 T184 | T120 T183 T184 | T120 T183 T184 | T323 T327 T328 | T323 T327 T328 | T323 T327 T97 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T323 T327 T328 | T2 T6 T13 | T67 T323 T232 | T138 T329 T139 | T266 T288 T151 | T265 T266 T68 | T172 T120 T335 | T120 T183 T184 | T5 T307 T144 | T5 T307 T144 | T307 T144 T329 | T307 T144 T329 | T5 T307 T144 | T329 T330 T331 | T324 T325 T329 | T329 T330 T331 | T329 T330 T331 | T120 T183 T184 | T120 T183 T184 | T120 T183 T184 | T326 T120 T143 | T120 T183 T184 | T329 T330 T331 | T336 T329 T337 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T329 T330 T331 | T336 T329 T337 | T329 T330 T331 | T336 T329 T337 | T329 T330 T331
318 end
319
320 //////////////
321 // Gateways //
322 //////////////
323
324 // Synchronize all incoming interrupt requests.
325 logic [NumSrc-1:0] intr_src_synced;
326 prim_flop_2sync #(
327 .Width(NumSrc)
328 ) u_prim_flop_2sync (
329 .clk_i,
330 .rst_ni,
331 .d_i(intr_src_i),
332 .q_o(intr_src_synced)
333 );
334
335 rv_plic_gateway #(
336 .N_SOURCE (NumSrc)
337 ) u_gateway (
338 .clk_i,
339 .rst_ni,
340
341 .src_i (intr_src_synced),
342 .le_i (LevelEdgeTrig),
343
344 .claim_i (claim),
345 .complete_i (complete),
346
347 .ip_o (ip)
348 );
349
350 ///////////////////////////////////
351 // Target interrupt notification //
352 ///////////////////////////////////
353 for (genvar i = 0 ; i < NumTarget ; i++) begin : gen_target
354 rv_plic_target #(
355 .N_SOURCE (NumSrc),
356 .MAX_PRIO (MAX_PRIO)
357 ) u_target (
358 .clk_i,
359 .rst_ni,
360
361 .ip_i (ip),
362 .ie_i (ie[i]),
363
364 .prio_i (prio),
365 .threshold_i (threshold[i]),
366
367 .irq_o (irq_o[i]),
368 .irq_id_o (irq_id_o[i])
369
370 );
371 end
372
373 ////////////
374 // Alerts //
375 ////////////
376
377 logic [NumAlerts-1:0] alert_test, alerts;
378
379 1/1 assign alert_test = {
Tests: T2 T5 T6